Fix Kconfig style
Remove spaces from Kconfig files Add TABs Replace help => ---help---
This commit is contained in:
simbit18
Xiang Xiao
parent
237087f61a
commit
583f025422
@ -92,134 +92,136 @@ config ARMV8R_NONMASKABLE_FIQ
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default n
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config ARMV8R_HAVE_L2CC
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bool
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default n
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---help---
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Selected by the configuration tool if the architecture supports any
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kind of L2 cache.
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bool
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default n
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---help---
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Selected by the configuration tool if the architecture supports any
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kind of L2 cache.
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config ARMV8R_HAVE_L2CC_PL310
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bool
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default n
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select ARMV8R_HAVE_L2CC
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---help---
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Set by architecture-specific code if the hardware supports a PL310
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r3p2 L2 cache (only version r3p2 is supported).
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bool
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default n
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select ARMV8R_HAVE_L2CC
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---help---
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Set by architecture-specific code if the hardware supports a PL310
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r3p2 L2 cache (only version r3p2 is supported).
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if ARMV8R_HAVE_L2CC
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menu "L2 Cache Configuration"
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config ARMV8R_L2CC_PL310
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bool "ARMv8-R L2CC P310 Support"
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default n
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depends on ARMV8R_HAVE_L2CC_PL310
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select ARCH_L2CACHE
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---help---
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Enable the 2 Cache Controller (L2CC) is based on the L2CC-PL310 ARM
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multi-way cache macrocell, version r3p2. The addition of an on-chip
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secondary cache, also referred to as a Level 2 or L2 cache, is a
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method of improving the system performance when significant memory
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traffic is generated by the processor.
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bool "ARMv8-R L2CC P310 Support"
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default n
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depends on ARMV8R_HAVE_L2CC_PL310
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select ARCH_L2CACHE
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---help---
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Enable the 2 Cache Controller (L2CC) is based on the L2CC-PL310 ARM
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multi-way cache macrocell, version r3p2. The addition of an on-chip
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secondary cache, also referred to as a Level 2 or L2 cache, is a
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method of improving the system performance when significant memory
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traffic is generated by the processor.
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if ARCH_L2CACHE
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if ARMV8R_L2CC_PL310
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config PL310_LOCKDOWN_BY_MASTER
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bool "PL310 Lockdown by Master"
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default n
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bool "PL310 Lockdown by Master"
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default n
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config PL310_LOCKDOWN_BY_LINE
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bool "PL310 Lockdown by Line"
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default n
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bool "PL310 Lockdown by Line"
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default n
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config PL310_ADDRESS_FILTERING
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bool "PL310 Address Filtering by Line"
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default n
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bool "PL310 Address Filtering by Line"
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default n
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config PL310_TRCR
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bool "PL310 TRCR set by usr"
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default n
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bool "PL310 TRCR set by usr"
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default n
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if PL310_TRCR
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config PL310_TRCR_TSETLAT
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int "PL310 TRCR setup latency"
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default 1
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int "PL310 TRCR setup latency"
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default 1
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config PL310_TRCR_TRDLAT
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int "PL310 TRCR read access latency"
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default 1
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int "PL310 TRCR read access latency"
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default 1
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config PL310_TRCR_TWRLAT
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int "PL310 TRCR write access latency"
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default 1
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int "PL310 TRCR write access latency"
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default 1
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endif # PL310_TRCR
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config PL310_DRCR
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bool "PL310 DRCR set by usr"
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default n
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bool "PL310 DRCR set by usr"
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default n
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if PL310_DRCR
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config PL310_DRCR_DSETLAT
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int "PL310 DRCR setup latency"
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default 1
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int "PL310 DRCR setup latency"
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default 1
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config PL310_DRCR_DRDLAT
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int "PL310 DRCR read access latency"
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default 1
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int "PL310 DRCR read access latency"
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default 1
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config PL310_DRCR_DWRLAT
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int "PL310 DRCR write access latency"
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default 1
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int "PL310 DRCR write access latency"
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default 1
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endif # PL310_DRCR
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endif # ARMV8R_L2CC_PL310
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choice
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prompt "L2 Cache Associativity"
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default ARMV8R_ASSOCIATIVITY_8WAY
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depends on ARCH_L2CACHE
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---help---
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This choice specifies the associativity of L2 cache in terms of the
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number of ways. This value could be obtained by querying cache
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configuration registers. However, by defining a configuration
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setting instead, we can avoid using RAM memory to hold information
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about properties of the memory.
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prompt "L2 Cache Associativity"
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default ARMV8R_ASSOCIATIVITY_8WAY
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depends on ARCH_L2CACHE
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---help---
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This choice specifies the associativity of L2 cache in terms of the
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number of ways. This value could be obtained by querying cache
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configuration registers. However, by defining a configuration
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setting instead, we can avoid using RAM memory to hold information
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about properties of the memory.
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config ARMV8R_ASSOCIATIVITY_8WAY
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bool "8-Way Associativity"
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bool "8-Way Associativity"
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config ARMV8R_ASSOCIATIVITY_16WAY
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bool "16-Way Associativity"
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bool "16-Way Associativity"
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endchoice # L2 Cache Associativity
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choice
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prompt "L2 Cache Way Size"
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default ARMV8R_WAYSIZE_16KB
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depends on ARCH_L2CACHE
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---help---
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This choice specifies size of each way. This value can be obtained
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by querying cache configuration registers. However, by defining a
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configuration setting instead, we can avoid using RAM memory to hold
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information
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prompt "L2 Cache Way Size"
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default ARMV8R_WAYSIZE_16KB
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depends on ARCH_L2CACHE
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---help---
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This choice specifies size of each way. This value can be obtained
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by querying cache configuration registers. However, by defining a
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configuration setting instead, we can avoid using RAM memory to hold
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information
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config ARMV8R_WAYSIZE_16KB
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bool "16 KiB"
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bool "16 KiB"
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config ARMV8R_WAYSIZE_32KB
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bool "32 KiB"
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bool "32 KiB"
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config ARMV8R_WAYSIZE_64KB
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bool "64 KiB"
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bool "64 KiB"
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config ARMV8R_WAYSIZE_128KB
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bool "128 KiB"
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bool "128 KiB"
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config ARMV8R_WAYSIZE_256KB
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bool "256 KiB"
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bool "256 KiB"
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config ARMV8R_WAYSIZE_512KB
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bool "512 KiB"
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bool "512 KiB"
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endchoice # L2 Cache Way Size
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endif # ARCH_L2CACHE
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@ -1112,9 +1112,9 @@ config ARCH_BOARD_MIZAR32A
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depends on ARCH_CHIP_AT32UC3A0512
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select ARCH_HAVE_LEDS
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---help---
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This is a port of NuttX for the Mizar32-A board designed by SimpleMachines,
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Italy. The board is based on the AT32UC3A0512 MCU and uses avr32-gcc
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version 4.4.7 for its build on GNU/Linux.
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This is a port of NuttX for the Mizar32-A board designed by SimpleMachines,
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Italy. The board is based on the AT32UC3A0512 MCU and uses avr32-gcc
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version 4.4.7 for its build on GNU/Linux.
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config ARCH_BOARD_MOTEINO_MEGA
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bool "LowPowerLab MoteinoMEGA"
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@ -8,10 +8,10 @@ choice
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prompt "Console Mode"
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default CSK6_CONSOLE_UART0
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config CSK6_CONSOLE_UART0
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bool "USART0 is a console port"
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select USART0_SERIALDRIVER
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config CSK6_CONSOLE_UART0
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bool "USART0 is a console port"
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select USART0_SERIALDRIVER
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#TODO add support other port
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endchoice # USART0 Mode
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endif
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@ -1534,7 +1534,7 @@ config SHT4X_I2C_FREQUENCY
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config SHT4X_I2C_ADDR
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hex "SHT4X I2C address"
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default 0x44
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range 0x44 0x46
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range 0x44 0x46
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---help---
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Enables debug features for the SHT4X
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@ -1718,34 +1718,34 @@ config SENSORS_LTR308_THREAD_STACKSIZE
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endif # SENSORS_LTR308
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config SENSORS_AMG88XX
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bool "AMG88xx infrared array sensor"
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default n
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select I2C
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---help---
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Enable driver support for AMG88xx infrared array sensor.
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bool "AMG88xx infrared array sensor"
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default n
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select I2C
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---help---
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Enable driver support for AMG88xx infrared array sensor.
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if SENSORS_AMG88XX
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choice
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prompt "AMG88xx AD_SELECT value"
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default SENSOR_AMG88XX_AD_SELECT_0
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---help---
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AD SELECT sets the amg88xx i2c address
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AD_SELECT tied to GND -> sensor address 0x68
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AD_SELECT tied to VCC -> sensor address 0x69
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prompt "AMG88xx AD_SELECT value"
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default SENSOR_AMG88XX_AD_SELECT_0
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---help---
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AD SELECT sets the amg88xx i2c address
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AD_SELECT tied to GND -> sensor address 0x68
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AD_SELECT tied to VCC -> sensor address 0x69
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config SENSOR_AMG88XX_AD_SELECT_0
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bool "AD_SELECT tied to GND"
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config SENSOR_AMG88XX_AD_SELECT_0
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bool "AD_SELECT tied to GND"
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config SENSOR_AMG88XX_AD_SELECT_1
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bool "AD_SELECT tied to VCC"
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config SENSOR_AMG88XX_AD_SELECT_1
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bool "AD_SELECT tied to VCC"
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endchoice
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config SENSOR_AMG88XX_ADDR
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hex
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default 0x68 if SENSOR_AMG88XX_AD_SELECT_0
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default 0x69 if SENSOR_AMG88XX_AD_SELECT_1
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hex
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default 0x68 if SENSOR_AMG88XX_AD_SELECT_0
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default 0x69 if SENSOR_AMG88XX_AD_SELECT_1
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endif # SENSORS_AMG88XX
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@ -13,8 +13,8 @@ config FS_V9FS
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if FS_V9FS
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config V9FS_DEFAULT_MSIZE
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int "V9FS Default message max size"
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default 65536
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int "V9FS Default message max size"
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default 65536
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config V9FS_VIRTIO_9P
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bool "Virtio 9P support"
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@ -1979,7 +1979,7 @@ config PID_INITIAL_COUNT
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config SCHED_EVENTS
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bool "Schedule Event objects"
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default n
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help
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This option enables event objects. Threads may wait on event
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objects for specific events, but both threads and ISRs may deliver
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events to event objects.
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---help---
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This option enables event objects. Threads may wait on event
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objects for specific events, but both threads and ISRs may deliver
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events to event objects.
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