Finish PWM pulse count configuration
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4287 42af7a65-404d-4744-a932-0658087f49c3
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@ -169,7 +169,7 @@ static int pwm_interrupt(struct stm32_pwmtimer_s *priv);
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#if defined(CONFIG_STM32_TIM1_PWM)
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static int pwm_tim1interrupt(int irq, void *context);
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#endif
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#if defined(CONFIG_STM32_TIM1_PWM)
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#if defined(CONFIG_STM32_TIM8_PWM)
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static int pwm_tim8interrupt(int irq, void *context);
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#endif
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#endif
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@ -906,12 +906,12 @@ static int pwm_interrupt(struct stm32_pwmtimer_s *priv)
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{
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/* Verify that this is an update interrupt. Nothing else is expected. */
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pwmllvdbg("Update interrupt: %04x\n", pwm_getreg(STM32_GTIM_SR_OFFSET));
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DEBUGASSERT((pwm_getreg(STM32_GTIM_SR_OFFSET) & ATIM_SR_UIF) != 0);
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pwmllvdbg("Update interrupt: %04x\n", pwm_getreg(priv, STM32_GTIM_SR_OFFSET));
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DEBUGASSERT((pwm_getreg(priv, STM32_GTIM_SR_OFFSET) & ATIM_SR_UIF) != 0);
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/* Disable further interrupts and stop the timer */
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(void)pwm_stop((FAR struct pwm_lowerhalf_s *)priv)
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(void)pwm_stop((FAR struct pwm_lowerhalf_s *)priv);
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/* Then perform the callback into the upper half driver */
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@ -2163,7 +2163,7 @@ static int pic32mx_interrupt(int irq, void *context)
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usbir = pic32mx_getreg(PIC32MX_USB_IR) & pic32mx_getreg(PIC32MX_USB_IE);
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otgir = pic32mx_getreg(PIC32MX_USBOTG_IR) & pic32mx_getreg(PIC32MX_USBOTG_IE);
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usbtrace(TRACE_INTENTRY(PIC32MX_TRACEINTID_INTERRUPT), usbir|otgir);
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usbtrace(TRACE_INTENTRY(PIC32MX_TRACEINTID_INTERRUPT), usbir | otgir);
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#ifdef CONFIG_USBOTG
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/* Session Request Protocol (SRP) Time Out Check */
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@ -2396,7 +2396,7 @@ static int pic32mx_interrupt(int irq, void *context)
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interrupt_exit:
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up_clrpend_irq(PIC32MX_IRQSRC_USB);
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usbtrace(TRACE_INTEXIT(PIC32MX_TRACEINTID_INTERRUPT), usbir | usbotg);
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usbtrace(TRACE_INTEXIT(PIC32MX_TRACEINTID_INTERRUPT), usbir | otgir);
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return OK;
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}
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