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Basic bring-up of the STM3240G-EVAL board is complete

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4138 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2011-12-06 19:31:28 +00:00
parent 7b634d851d
commit 65bbfd2a02
3 changed files with 11 additions and 9 deletions
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2
ChangeLog
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@ -2238,3 +2238,5 @@
Mikhail Bychek).
* configs/stm3210e-eval/src/up_lcd.c: Fix banding problem on the R61580
LCD
* configs/stm3240g-eval/ostest: The basic STM32F40xx bringup is functional
(11/12/06) and passes the OS test.

4
arch/arm/src/stm32/stm32_gpio.c
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@ -515,8 +515,8 @@ int stm32_configgpio(uint32_t cfgset)
}
regval = getreg32(base + STM32_GPIO_OSPEED_OFFSET);
regval &= ~GPIO_OSPEED_MASK(pos);
regval |= (setting << GPIO_OSPEED_SHIFT(pos));
regval &= ~GPIO_OSPEED_MASK(pin);
regval |= (setting << GPIO_OSPEED_SHIFT(pin));
putreg32(regval, base + STM32_GPIO_OSPEED_OFFSET);
/* Set push-pull/open-drain (Only outputs and alternate function pins) */

12
configs/stm3240g-eval/include/board.h
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@ -124,16 +124,16 @@
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE1_HCLKd2 /* PCLK2 = HCLK / 2 */
#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2)
/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE2_HCLKd4 /* PCLK1 = HCLK / 4 */
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4)
/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2)
/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
* otherwise frequency is 2xAPBx.
* Note: TIM1,8 are on APB2, others on APB1