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STM32 ADC driver update

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4211 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2011-12-22 00:31:47 +00:00
parent c0db417435
commit 7480e0c3cb
5 changed files with 11 additions and 13 deletions
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4
configs/hymini-stm32v/include/board.h
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@ -90,8 +90,8 @@
/* APB2 timers 1 and 8 will receive PCLK2. */ /* APB2 timers 1 and 8 will receive PCLK2. */
#define STM32_APB1_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) #define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY)
#define STM32_APB1_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) #define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY)
/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ /* APB1 clock (PCLK1) is HCLK/2 (36MHz) */

4
configs/stm3210e-eval/include/board.h
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@ -86,8 +86,8 @@
/* APB2 timers 1 and 8 will receive PCLK2. */ /* APB2 timers 1 and 8 will receive PCLK2. */
#define STM32_APB1_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) #define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY)
#define STM32_APB1_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) #define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY)
/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ /* APB1 clock (PCLK1) is HCLK/2 (36MHz) */

10
configs/stm3210e-eval/src/up_adc.c
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@ -82,13 +82,13 @@
* Private Data * Private Data
************************************************************************************/ ************************************************************************************/
/* Identifying number of each ADC channel: Variable Resistor , BNC_CN5 and BNC_CN3 */ /* Identifying number of each ADC channel: Variable Resistor and BNC_CN5 */
static const uint8_t g_chanlist[ADC_NCHANNELS] = {14, 10}; static const uint8_t g_chanlist[ADC_NCHANNELS] = {14, 11};
/* Configurations of pins used byte each ADC channels */ /* Configurations of pins used byte each ADC channels */
static const uint32_t g_pinlist[ADC_NCHANNELS] = {GPIO_ADC1_IN14 , GPIO_ADC1_IN10}; static const uint32_t g_pinlist[ADC_NCHANNELS] = {GPIO_ADC1_IN14 , GPIO_ADC1_IN11};
/************************************************************************************ /************************************************************************************
* Private Functions * Private Functions
@ -114,13 +114,11 @@ int adc_devinit(void)
int ret; int ret;
int i; int i;
avdbg("Entry\n");
/* Configure the pins as analog inputs for the selected channels */ /* Configure the pins as analog inputs for the selected channels */
for(i = 0; i < ADC_NCHANNELS; i++) for(i = 0; i < ADC_NCHANNELS; i++)
{ {
stm32_configgpio(g_chanlist[i]); stm32_configgpio(g_pinlist[i]);
} }
/* Call stm32_adcinitialize() to get an instance of the ADC interface */ /* Call stm32_adcinitialize() to get an instance of the ADC interface */

2
configs/stm3240g-eval/include/board.h
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@ -146,7 +146,7 @@
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ #define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) #define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2)
/* Timers driven from APB12will be twice PCLK2 */ /* Timers driven from APB2 will be twice PCLK2 */
#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) #define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY)
#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK1_FREQUENCY) #define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK1_FREQUENCY)

4
configs/vsn/include/board.h
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@ -99,8 +99,8 @@
/* APB2 timers 1 and 8 will receive PCLK2. */ /* APB2 timers 1 and 8 will receive PCLK2. */
#define STM32_APB1_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) #define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY)
#define STM32_APB1_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) #define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY)
/* APB1 clock (PCLK1) is HCLK (36MHz) */ /* APB1 clock (PCLK1) is HCLK (36MHz) */