Extend the RISC-V PMP functionality
- Add test for mode support, which is architecture dependent - Add tests for address alignment and region size - Add option to query for access rights - The function goes through every PMP entry and tests if an address range from [base, base+size] has been configured for desired access rights. - If several PMP entries match the range and access rights, the information is combined - End result is either no access, a partial match was found, or a full match was found. Details about the partial match are not provided. The intent for testing access rights and not just blindly applying them is a case where they are already set in e.g. a bootloader. In this case, nothing should be done, unless the configuration does not match, in which case the software must not continue further.
This commit is contained in:
Ville Juven
Xiang Xiao
parent
8a4881c4e5
commit
81188d9c94
@ -101,6 +101,7 @@ config ARCH_CHIP_MPFS
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select ARCH_HAVE_RESET
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select ARCH_HAVE_SPI_CS_CONTROL
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select ARCH_HAVE_PWM_MULTICHAN
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select PMP_HAS_LIMITED_FEATURES
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---help---
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MicroChip Polarfire processor (RISC-V 64bit core with GCVX extensions).
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@ -188,6 +189,29 @@ config ARCH_MMU_TYPE_SV39
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bool
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default n
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# MPU has certain architecture dependent configurations, which are presented
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# here. Default is that the full RISC-V PMP specification is supported.
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config PMP_HAS_LIMITED_FEATURES
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bool
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default n
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config ARCH_MPU_MIN_BLOCK_SIZE
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int "Minimum MPU (PMP) block size"
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default 4 if !PMP_HAS_LIMITED_FEATURES
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config ARCH_MPU_HAS_TOR
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bool "PMP supports TOR"
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default y if !PMP_HAS_LIMITED_FEATURES
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config ARCH_MPU_HAS_NO4
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bool "PMP supports NO4"
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default y if !PMP_HAS_LIMITED_FEATURES
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config ARCH_MPU_HAS_NAPOT
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bool "PMP supports NAPOT"
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default y if !PMP_HAS_LIMITED_FEATURES
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source "arch/risc-v/src/opensbi/Kconfig"
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source "arch/risc-v/src/common/Kconfig"
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@ -346,6 +346,7 @@
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#define PMPCFG_R (1 << 0) /* readable ? */
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#define PMPCFG_W (1 << 1) /* writeable ? */
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#define PMPCFG_X (1 << 2) /* excutable ? */
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#define PMPCFG_RWX_MASK (7 << 0) /* access rights mask */
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#define PMPCFG_A_OFF (0 << 3) /* null region (disabled) */
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#define PMPCFG_A_TOR (1 << 3) /* top of range */
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#define PMPCFG_A_NA4 (2 << 3) /* naturally aligned four-byte region */
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@ -91,6 +91,12 @@
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# endif
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#endif
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/* Return values from riscv_check_pmp_access */
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#define PMP_ACCESS_OFF (0) /* Access for area not set */
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#define PMP_ACCESS_DENIED (-1) /* Access set and denied */
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#define PMP_ACCESS_FULL (1) /* Access set and allowed */
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/****************************************************************************
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* Public Types
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****************************************************************************/
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@ -177,8 +183,12 @@ void riscv_restorefpu(const uintptr_t *regs);
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/* RISC-V PMP Config ********************************************************/
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void riscv_config_pmp_region(uintptr_t region, uintptr_t attr,
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uintptr_t base, uintptr_t size);
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int riscv_config_pmp_region(uintptr_t region, uintptr_t attr,
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uintptr_t base, uintptr_t size);
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int riscv_check_pmp_access(uintptr_t attr, uintptr_t base, uintptr_t size);
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int riscv_configured_pmp_regions(void);
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int riscv_next_free_pmp_region(void);
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/* Power management *********************************************************/
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@ -22,6 +22,9 @@
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* Included Files
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****************************************************************************/
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#include <stdbool.h>
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#include <nuttx/compiler.h>
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#include <nuttx/config.h>
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#include <nuttx/arch.h>
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#include <arch/csr.h>
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@ -32,6 +35,18 @@
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* Pre-processor Definitions
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****************************************************************************/
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/* Minimum supported block size */
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#if !defined CONFIG_ARCH_MPU_MIN_BLOCK_SIZE
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#define MIN_BLOCK_SIZE (__riscv_xlen / 8)
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#else
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#define MIN_BLOCK_SIZE CONFIG_ARCH_MPU_MIN_BLOCK_SIZE
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#endif
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/* Address and block size alignment mask */
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#define BLOCK_ALIGN_MASK (MIN_BLOCK_SIZE - 1)
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#define PMP_CFG_BITS_CNT (8)
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#define PMP_CFG_FLAG_MASK (0xFF)
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@ -44,6 +59,361 @@
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reg |= attr << (offset * PMP_CFG_BITS_CNT); \
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} while(0);
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#define PMP_READ_REGION_FROM_REG(region, reg) \
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({ \
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uintptr_t tmp = READ_CSR(reg); \
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tmp >>= ((region % PMP_CFG_CNT_IN_REG) * PMP_CFG_BITS_CNT); \
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tmp &= PMP_CFG_FLAG_MASK; \
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tmp; \
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})
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#ifndef min
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#define min(a,b) ((a) < (b) ? (a) : (b))
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#endif
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#ifndef max
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#define max(a,b) ((a) > (b) ? (a) : (b))
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#endif
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/****************************************************************************
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* Private Types
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****************************************************************************/
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/* Helper structure for handling a PMP entry */
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struct pmp_entry_s
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{
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uintptr_t base; /* Base address of region */
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uintptr_t end; /* End address of region */
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uintptr_t size; /* Region size */
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uint8_t mode; /* Address matching mode */
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uint8_t rwx; /* Access rights */
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};
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typedef struct pmp_entry_s pmp_entry_t;
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: pmp_check_addrmatch_type
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*
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* Description:
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* Test if an address matching type is supported by the architecture.
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*
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* Input Parameters:
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* type - The type to test.
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*
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* Returned Value:
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* true if it is, false otherwise.
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*
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****************************************************************************/
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static bool pmp_check_addrmatch_type(uintptr_t type)
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{
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/* Parameter is potentially unused */
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UNUSED(type);
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#ifdef CONFIG_ARCH_MPU_HAS_TOR
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if (type == PMPCFG_A_TOR)
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{
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return true;
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}
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#endif
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#ifdef CONFIG_ARCH_MPU_HAS_NO4
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if (type == PMPCFG_A_NA4)
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{
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return true;
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}
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#endif
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#ifdef CONFIG_ARCH_MPU_HAS_NAPOT
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if (type == PMPCFG_A_NAPOT)
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{
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return true;
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}
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#endif
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/* None of the supported types match */
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return false;
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}
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/****************************************************************************
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* Name: pmp_check_region_attrs
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*
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* Description:
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* Test if the base address and size of region meet alignment requirements.
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*
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* Input Parameters:
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* base - The base address of the region.
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* size - The memory length of the region.
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*
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* Returned Value:
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* true if it is, false otherwise.
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*
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****************************************************************************/
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static bool pmp_check_region_attrs(uintptr_t base, uintptr_t size)
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{
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/* Check that the size is not too small */
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if (size < MIN_BLOCK_SIZE)
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{
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return false;
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}
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/* Check that the base address is aligned properly */
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if ((base & BLOCK_ALIGN_MASK) != 0)
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{
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return false;
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}
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/* Check that the size is aligned properly */
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if ((size & BLOCK_ALIGN_MASK) != 0)
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{
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return false;
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}
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return OK;
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}
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/****************************************************************************
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* Name: pmp_read_region_cfg
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*
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* Description:
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* Read PMP configuration for region
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*
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* Input Parameters:
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* region - Region number.
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*
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* Returned Value:
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* Configuration value from pmpcfg+region
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*
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****************************************************************************/
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static uintptr_t pmp_read_region_cfg(uintptr_t region)
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{
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# if (__riscv_xlen == 32)
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switch (region)
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{
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case 0 ... 3:
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return PMP_READ_REGION_FROM_REG(region, pmpcfg0);
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case 4 ... 7:
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return PMP_READ_REGION_FROM_REG(region, pmpcfg1);
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case 8 ... 11:
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return PMP_READ_REGION_FROM_REG(region, pmpcfg2);
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case 12 ... 15:
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return PMP_READ_REGION_FROM_REG(region, pmpcfg3);
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default:
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break;
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}
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# elif (__riscv_xlen == 64)
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switch (region)
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{
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case 0 ... 7:
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return PMP_READ_REGION_FROM_REG(region, pmpcfg0);
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case 8 ... 15:
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return PMP_READ_REGION_FROM_REG(region, pmpcfg2);
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default:
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break;
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}
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#endif
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/* Never executed */
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return 0;
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}
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/****************************************************************************
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* Name: pmp_read_addr
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*
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* Description:
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* Read address for region
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*
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* Input Parameters:
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* region - Region number.
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*
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* Returned Value:
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* Address value from pmpcfg+region
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*
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****************************************************************************/
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static uintptr_t pmp_read_addr(uintptr_t region)
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{
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switch (region)
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{
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case 0:
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return READ_CSR(pmpaddr0);
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case 1:
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return READ_CSR(pmpaddr1);
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case 2:
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return READ_CSR(pmpaddr2);
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case 3:
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return READ_CSR(pmpaddr3);
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case 4:
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return READ_CSR(pmpaddr4);
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case 5:
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return READ_CSR(pmpaddr5);
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case 6:
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return READ_CSR(pmpaddr6);
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case 7:
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return READ_CSR(pmpaddr7);
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case 8:
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return READ_CSR(pmpaddr8);
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case 9:
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return READ_CSR(pmpaddr9);
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case 10:
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return READ_CSR(pmpaddr10);
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case 11:
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return READ_CSR(pmpaddr11);
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case 12:
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return READ_CSR(pmpaddr12);
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case 13:
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return READ_CSR(pmpaddr13);
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case 14:
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return READ_CSR(pmpaddr14);
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case 15:
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return READ_CSR(pmpaddr15);
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default:
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break;
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}
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/* Never executed */
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return 0;
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}
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/****************************************************************************
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* Name: pmp_napot_decode
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*
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* Description:
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* Decode base and size from NAPOT value
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*
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* Input Parameters:
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* val - Value to decode.
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* base - Base out.
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* size - Size out.
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static void pmp_napot_decode(uintptr_t val, uintptr_t * base,
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uintptr_t * size)
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{
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uint64_t mask = (uint64_t)(-1) >> 1;
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uint64_t pot = __riscv_xlen + 2;
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while (mask)
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{
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if ((val & mask) == mask)
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{
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break;
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}
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pot--;
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mask >>= 1;
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}
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val &= ~mask;
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*base = (val << 2);
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*size = (1 << pot);
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}
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/****************************************************************************
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* Name: pmp_read
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*
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* Description:
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* Read PMP region into PMP entry
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*
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* Input Parameters:
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* region - Region number.
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* entry - Entry out
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static void pmp_read(uintptr_t region, pmp_entry_t * entry)
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{
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uintptr_t addr = 0;
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uintptr_t size = 0;
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uintptr_t mode = 0;
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uintptr_t rwx = 0;
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uintptr_t cfg = 0;
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addr = pmp_read_addr(region);
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cfg = pmp_read_region_cfg(region);
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mode = cfg & PMPCFG_A_MASK;
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rwx = cfg & PMPCFG_RWX_MASK;
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switch (mode)
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{
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case PMPCFG_A_TOR:
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addr <<= 2;
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/* TOR region, must peek into prior region for size */
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if (region == 0)
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{
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size = addr;
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}
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else
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{
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size = addr - pmp_read_addr(region - 1);
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}
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break;
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case PMPCFG_A_NA4:
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addr <<= 2;
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size = 4;
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break;
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case PMPCFG_A_NAPOT:
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pmp_napot_decode(addr, &addr, &size);
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break;
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default:
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break;
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}
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entry->base = addr;
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entry->end = addr + size;
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entry->size = size;
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entry->rwx = rwx;
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entry->mode = mode;
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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@ -63,17 +433,32 @@
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* and the size must be power-of-two according to the the PMP spec.
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*
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* Returned Value:
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* None.
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* 0 on succeess; negated error on failure
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*
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****************************************************************************/
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void riscv_config_pmp_region(uintptr_t region, uintptr_t attr,
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uintptr_t base, uintptr_t size)
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int riscv_config_pmp_region(uintptr_t region, uintptr_t attr,
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uintptr_t base, uintptr_t size)
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{
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uintptr_t addr = 0;
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uintptr_t cfg = 0;
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uintptr_t addr = 0;
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uintptr_t cfg = 0;
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uintptr_t type = (attr & PMPCFG_A_MASK);
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/* TODO: check the base address alignment and size */
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/* Check that the architecture supports address matching type */
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if (pmp_check_addrmatch_type(type) == false)
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{
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return -EINVAL;
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}
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/* Check the region attributes */
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if (pmp_check_region_attrs(base, size))
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{
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return -EINVAL;
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}
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/* Calculate new base address from type */
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addr = base >> 2;
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if (PMPCFG_A_NAPOT == (attr & PMPCFG_A_MASK))
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@ -81,6 +466,8 @@ void riscv_config_pmp_region(uintptr_t region, uintptr_t attr,
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addr |= (size - 1) >> 3;
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}
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/* Set the address value */
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switch (region)
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{
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case 0:
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@ -151,6 +538,8 @@ void riscv_config_pmp_region(uintptr_t region, uintptr_t attr,
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break;
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}
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/* Set the configuration register value */
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# if (__riscv_xlen == 32)
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switch (region)
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{
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@ -206,4 +595,165 @@ void riscv_config_pmp_region(uintptr_t region, uintptr_t attr,
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/* fence is needed when page-based virtual memory is implemented */
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__asm volatile("sfence.vma x0, x0" : : : "memory");
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return OK;
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}
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/****************************************************************************
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* Name: riscv_check_pmp_access
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*
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* Description:
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* This function will set the specific PMP region with the desired cfg.
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*
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* Input Parameters:
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* attr - The region configurations.
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* base - The base address of the region.
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* size - The memory length of the region.
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* For the NAPOT mode, the base address must aligned to the size boundary,
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* and the size must be power-of-two according to the the PMP spec.
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*
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* Returned Value:
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* 0 if access rights are not set at all
|
||||
* < 0 if access rights are set and match match partially
|
||||
* > 0 if access rights are set and match fully
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int riscv_check_pmp_access(uintptr_t attr, uintptr_t base, uintptr_t size)
|
||||
{
|
||||
pmp_entry_t entry;
|
||||
uintptr_t end;
|
||||
uintptr_t orgsize;
|
||||
unsigned int region;
|
||||
|
||||
/* Go through every single configured region and test the attributes */
|
||||
|
||||
attr = (attr & PMPCFG_RWX_MASK);
|
||||
end = base + size;
|
||||
orgsize = size;
|
||||
|
||||
for (region = 0; region < 16 && size > 0; region++)
|
||||
{
|
||||
/* Find matching configuration first */
|
||||
|
||||
pmp_read(region, &entry);
|
||||
|
||||
/* Check if any configuration at all */
|
||||
|
||||
if (entry.mode == PMPCFG_A_OFF)
|
||||
{
|
||||
continue;
|
||||
}
|
||||
|
||||
/* Does this address range match ? Take partial matches into account.
|
||||
*
|
||||
* There are four possibilities:
|
||||
* 1: Full match; region inside mapped area
|
||||
* 2: Partial match; mapped area inside region
|
||||
* 3: Partial match; base inside mapped region, end outside
|
||||
* 4: Partial match; base outside mapped region, end inside
|
||||
*/
|
||||
|
||||
if ((base >= entry.base && end <= entry.end) ||
|
||||
(base <= entry.base && end >= entry.end) ||
|
||||
(base >= entry.base && base <= entry.end) ||
|
||||
(end >= entry.base && end <= entry.end))
|
||||
{
|
||||
/* Found a matching splice, check rights */
|
||||
|
||||
if ((entry.rwx & attr) == attr)
|
||||
{
|
||||
/* Found matching region that allows access */
|
||||
|
||||
size -= min(end, entry.end) - max(base, entry.base);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Found matching region that does not allow access */
|
||||
|
||||
return PMP_ACCESS_DENIED;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Check if nothing configured at all ? */
|
||||
|
||||
if (size == orgsize)
|
||||
{
|
||||
return PMP_ACCESS_OFF;
|
||||
}
|
||||
|
||||
/* If size is non-positive, the requested range is accessible */
|
||||
|
||||
if (size <= 0)
|
||||
{
|
||||
return PMP_ACCESS_FULL;
|
||||
}
|
||||
|
||||
/* The requested range is either fully or partially inaccessible */
|
||||
|
||||
return PMP_ACCESS_DENIED;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: riscv_configured_pmp_regions
|
||||
*
|
||||
* Description:
|
||||
* Count amount of configured PMP regions, note: is not atomic
|
||||
*
|
||||
* Input Parameters:
|
||||
*
|
||||
* Returned Value:
|
||||
* Amount of configured PMP regions
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int riscv_configured_pmp_regions(void)
|
||||
{
|
||||
pmp_entry_t entry;
|
||||
unsigned int region;
|
||||
int ret = 0;
|
||||
|
||||
for (region = 0; region < 16; region++)
|
||||
{
|
||||
pmp_read(region, &entry);
|
||||
|
||||
if (entry.mode != PMPCFG_A_OFF)
|
||||
{
|
||||
ret++;
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: riscv_next_free_pmp_region
|
||||
*
|
||||
* Description:
|
||||
* Returns next free PMP region, note: is not atomic
|
||||
*
|
||||
* Input Parameters:
|
||||
*
|
||||
* Returned Value:
|
||||
* Next free PMP region, or -1 if none found
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int riscv_next_free_pmp_region(void)
|
||||
{
|
||||
pmp_entry_t entry;
|
||||
unsigned int region;
|
||||
|
||||
for (region = 0; region < 16; region++)
|
||||
{
|
||||
pmp_read(region, &entry);
|
||||
|
||||
if (entry.mode == PMPCFG_A_OFF)
|
||||
{
|
||||
return region;
|
||||
}
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
@ -312,3 +312,17 @@ config MPFS_DMA
|
||||
menu "MPFS Others"
|
||||
|
||||
endmenu
|
||||
|
||||
# Override the default values for MPU / PMP parameters here
|
||||
|
||||
config ARCH_MPU_MIN_BLOCK_SIZE
|
||||
default 4096
|
||||
|
||||
config ARCH_MPU_HAS_TOR
|
||||
default n
|
||||
|
||||
config ARCH_MPU_HAS_NO4
|
||||
default n
|
||||
|
||||
config ARCH_MPU_HAS_NAPOT
|
||||
default y
|
||||
|
||||
@ -39,11 +39,20 @@
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define PMP_UFLASH_FLAGS (PMPCFG_A_NAPOT | PMPCFG_X | PMPCFG_R)
|
||||
#define PMP_USRAM_FLAGS (PMPCFG_A_NAPOT | PMPCFG_W | PMPCFG_R)
|
||||
|
||||
#define UFLASH_START (uintptr_t)&__uflash_start
|
||||
#define UFLASH_SIZE (uintptr_t)&__uflash_size
|
||||
#define USRAM_START (uintptr_t)&__usram_start
|
||||
#define USRAM_SIZE (uintptr_t)&__usram_size
|
||||
|
||||
/* Physical and virtual addresses to page tables (vaddr = paddr mapping) */
|
||||
|
||||
#define PGT_BASE_PADDR (uint64_t)&m_l1_pgtable
|
||||
#define PGT_L1_PBASE (uint64_t)&m_l1_pgtable
|
||||
#define PGT_L2_PBASE (uint64_t)&m_l2_pgtable
|
||||
#define PGT_L3_PBASE (uint64_t)&m_l3_pgtable
|
||||
#define PGT_L1_VBASE PGT_L1_PBASE
|
||||
#define PGT_L2_VBASE PGT_L2_PBASE
|
||||
#define PGT_L3_VBASE PGT_L3_PBASE
|
||||
|
||||
@ -52,6 +61,11 @@
|
||||
#define MMU_UFLASH_FLAGS (PTE_R | PTE_X | PTE_U | PTE_G)
|
||||
#define MMU_USRAM_FLAGS (PTE_R | PTE_W | PTE_U | PTE_G)
|
||||
|
||||
/* Kernel RAM needs to be opened (the page tables) */
|
||||
|
||||
#define KSRAM_START (uintptr_t)&__ksram_start
|
||||
#define KSRAM_SIZE (uintptr_t)&__ksram_size
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
@ -178,9 +192,8 @@ static void configure_mpu(void)
|
||||
/* Configure the PMP to permit user-space access to its ROM and RAM.
|
||||
*
|
||||
* Note: PMP by default revokes access, thus if different privilege modes
|
||||
* are in use (mstatus.mprv is set), the the user space _must_ be granted
|
||||
* access here, otherwise an exception will fire when the user space task
|
||||
* is started.
|
||||
* are in use, the user space _must_ be granted access here, otherwise
|
||||
* an exception will fire when the user space task is started.
|
||||
*
|
||||
* Note: according to the Polarfire reference manual, address bits [1:0]
|
||||
* are not considered (due to 4 octet alignment), so strictly they don't
|
||||
@ -198,19 +211,46 @@ static void configure_mpu(void)
|
||||
*
|
||||
*/
|
||||
|
||||
riscv_config_pmp_region(0, PMPCFG_A_NAPOT | PMPCFG_X | PMPCFG_R,
|
||||
(uintptr_t)&__uflash_start,
|
||||
(uintptr_t)&__uflash_size);
|
||||
int ret;
|
||||
int idx;
|
||||
|
||||
riscv_config_pmp_region(1, PMPCFG_A_NAPOT | PMPCFG_W | PMPCFG_R,
|
||||
(uintptr_t)&__usram_start,
|
||||
(uintptr_t)&__usram_size);
|
||||
/* First, test access to user flash */
|
||||
|
||||
ret = riscv_check_pmp_access(PMP_UFLASH_FLAGS, UFLASH_START, UFLASH_SIZE);
|
||||
|
||||
/* No access or partial access means we must crash */
|
||||
|
||||
DEBUGASSERT(ret != PMP_ACCESS_DENIED);
|
||||
|
||||
if (ret == PMP_ACCESS_OFF)
|
||||
{
|
||||
idx = riscv_next_free_pmp_region();
|
||||
DEBUGASSERT(idx >= 0);
|
||||
riscv_config_pmp_region(idx, PMP_UFLASH_FLAGS, UFLASH_START,
|
||||
UFLASH_SIZE);
|
||||
}
|
||||
|
||||
/* Then, test access to user RAM */
|
||||
|
||||
ret = riscv_check_pmp_access(PMP_USRAM_FLAGS, USRAM_START, USRAM_SIZE);
|
||||
DEBUGASSERT(ret != PMP_ACCESS_DENIED);
|
||||
if (ret == PMP_ACCESS_OFF)
|
||||
{
|
||||
idx = riscv_next_free_pmp_region();
|
||||
DEBUGASSERT(idx >= 0);
|
||||
riscv_config_pmp_region(idx, PMP_USRAM_FLAGS, USRAM_START, USRAM_SIZE);
|
||||
}
|
||||
|
||||
/* The supervisor must have access to the page tables */
|
||||
|
||||
riscv_config_pmp_region(2, PMPCFG_A_NAPOT | PMPCFG_W | PMPCFG_R,
|
||||
(uintptr_t)&__ksram_start,
|
||||
(uintptr_t)&__ksram_size);
|
||||
ret = riscv_check_pmp_access(PMP_USRAM_FLAGS, KSRAM_START, KSRAM_SIZE);
|
||||
DEBUGASSERT(ret != PMP_ACCESS_DENIED);
|
||||
if (ret == PMP_ACCESS_OFF)
|
||||
{
|
||||
idx = riscv_next_free_pmp_region();
|
||||
DEBUGASSERT(idx >= 0);
|
||||
riscv_config_pmp_region(idx, PMP_USRAM_FLAGS, KSRAM_START, KSRAM_SIZE);
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -228,24 +268,22 @@ static void configure_mmu(void)
|
||||
|
||||
/* Setup the L3 references for executable memory */
|
||||
|
||||
mmu_ln_map_region(3, PGT_L3_VBASE, (uintptr_t)&__uflash_start,
|
||||
(uintptr_t)&__uflash_start, (uintptr_t)&__uflash_size,
|
||||
MMU_UFLASH_FLAGS);
|
||||
mmu_ln_map_region(3, PGT_L3_VBASE, UFLASH_START, UFLASH_START,
|
||||
UFLASH_SIZE, MMU_UFLASH_FLAGS);
|
||||
|
||||
/* Setup the L3 references for data memory */
|
||||
|
||||
mmu_ln_map_region(3, PGT_L3_VBASE, (uintptr_t)&__usram_start,
|
||||
(uintptr_t)&__usram_start, (uintptr_t)&__usram_size,
|
||||
MMU_USRAM_FLAGS);
|
||||
mmu_ln_map_region(3, PGT_L3_VBASE, USRAM_START, USRAM_START,
|
||||
USRAM_SIZE, MMU_USRAM_FLAGS);
|
||||
|
||||
/* Setup the L2 and L1 references */
|
||||
|
||||
mmu_ln_setentry(2, PGT_L2_VBASE, PGT_L3_PBASE, PGT_L3_VBASE, PTE_G);
|
||||
mmu_ln_setentry(1, PGT_BASE_PADDR, PGT_L2_PBASE, PGT_L2_VBASE, PTE_G);
|
||||
mmu_ln_setentry(1, PGT_L1_VBASE, PGT_L2_PBASE, PGT_L2_VBASE, PTE_G);
|
||||
|
||||
/* Enable MMU */
|
||||
|
||||
mmu_enable(PGT_BASE_PADDR, 0);
|
||||
mmu_enable(PGT_L1_PBASE, 0);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_BUILD_PROTECTED */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user