LPC43xx: Add Ethernet support. From Ilya Averyanov
This commit is contained in:
Ilya Averyanov
Gregory Nutt
parent
fdfaf9aa09
commit
a3bc46f629
@ -163,6 +163,151 @@ config LPC43_ETHERNET
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bool "Ethernet"
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default n
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if LPC43_ETHERNET
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menu "Ethernet MAC configuration"
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config LPC43_PHYADDR
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int "PHY address"
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default 1
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---help---
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The 5-bit address of the PHY on the board. Default: 1
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config LPC43_PHYINIT
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bool "Board-specific PHY Initialization"
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default n
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---help---
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Some boards require specialized initialization of the PHY before it can be used.
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This may include such things as configuring GPIOs, resetting the PHY, etc. If
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LPC43_PHYINIT is defined in the configuration then the board specific logic must
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provide lpc43_phyinitialize(); The LPC43 Ethernet driver will call this function
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one time before it first uses the PHY.
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config LPC43_MII
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bool "Use MII interface"
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default n
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---help---
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Support Ethernet MII interface.
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config LPC43_AUTONEG
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bool "Use autonegotiation"
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default y
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---help---
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Use PHY autonegotiation to determine speed and mode
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config LPC43_ETHFD
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bool "Full duplex"
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default n
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depends on !LPC43_AUTONEG
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---help---
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If LPC43_AUTONEG is not defined, then this may be defined to select full duplex
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mode. Default: half-duplex
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config LPC43_ETH100MBPS
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bool "100 Mbps"
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default n
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depends on !LPC43_AUTONEG
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---help---
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If LPC43_AUTONEG is not defined, then this may be defined to select 100 MBps
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speed. Default: 10 Mbps
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config LPC43_PHYSR
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int "PHY Status Register Address (decimal)"
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depends on LPC43_AUTONEG
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---help---
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This must be provided if LPC43_AUTONEG is defined. The PHY status register
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address may diff from PHY to PHY. This configuration sets the address of
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the PHY status register.
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config LPC43_PHYSR_ALTCONFIG
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bool "PHY Status Alternate Bit Layout"
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default n
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depends on LPC43_AUTONEG
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---help---
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Different PHYs present speed and mode information in different ways. Some
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will present separate information for speed and mode (this is the default).
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Those PHYs, for example, may provide a 10/100 Mbps indication and a separate
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full/half duplex indication. This options selects an alternative representation
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where speed and mode information are combined. This might mean, for example,
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separate bits for 10HD, 100HD, 10FD and 100FD.
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config LPC43_PHYSR_SPEED
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hex "PHY Speed Mask"
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depends on LPC43_AUTONEG && !LPC43_PHYSR_ALTCONFIG
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---help---
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This must be provided if LPC43_AUTONEG is defined. This provides bit mask
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for isolating the 10 or 100MBps speed indication.
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config LPC43_PHYSR_100MBPS
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hex "PHY 100Mbps Speed Value"
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depends on LPC43_AUTONEG && !LPC43_PHYSR_ALTCONFIG
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---help---
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This must be provided if LPC43_AUTONEG is defined. This provides the value
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of the speed bit(s) indicating 100MBps speed.
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config LPC43_PHYSR_MODE
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hex "PHY Mode Mask"
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depends on LPC43_AUTONEG && !LPC43_PHYSR_ALTCONFIG
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---help---
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This must be provided if LPC43_AUTONEG is defined. This provide bit mask
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for isolating the full or half duplex mode bits.
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config LPC43_PHYSR_FULLDUPLEX
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hex "PHY Full Duplex Mode Value"
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depends on LPC43_AUTONEG && !LPC43_PHYSR_ALTCONFIG
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---help---
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This must be provided if LPC43_AUTONEG is defined. This provides the
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value of the mode bits indicating full duplex mode.
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config LPC43_PHYSR_ALTMODE
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hex "PHY Mode Mask"
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depends on LPC43_AUTONEG && LPC43_PHYSR_ALTCONFIG
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---help---
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This must be provided if LPC43_AUTONEG is defined. This provide bit mask
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for isolating the speed and full/half duplex mode bits.
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config LPC43_PHYSR_10HD
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hex "10MBase-T Half Duplex Value"
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depends on LPC43_AUTONEG && LPC43_PHYSR_ALTCONFIG
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---help---
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This must be provided if LPC43_AUTONEG is defined. This is the value
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under the bit mask that represents the 10Mbps, half duplex setting.
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config LPC43_PHYSR_100HD
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hex "100Base-T Half Duplex Value"
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depends on LPC43_AUTONEG && LPC43_PHYSR_ALTCONFIG
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---help---
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This must be provided if LPC43_AUTONEG is defined. This is the value
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under the bit mask that represents the 100Mbps, half duplex setting.
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config LPC43_PHYSR_10FD
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hex "10Base-T Full Duplex Value"
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depends on LPC43_AUTONEG && LPC43_PHYSR_ALTCONFIG
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---help---
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This must be provided if LPC43_AUTONEG is defined. This is the value
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under the bit mask that represents the 10Mbps, full duplex setting.
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config LPC43_PHYSR_100FD
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hex "100Base-T Full Duplex Value"
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depends on LPC43_AUTONEG && LPC43_PHYSR_ALTCONFIG
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---help---
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This must be provided if LPC43_AUTONEG is defined. This is the value
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under the bit mask that represents the 100Mbps, full duplex setting.
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config LPC43_RMII
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bool
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default y if !LPC43_MII
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config LPC43_ETHERNET_REGDEBUG
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bool "Register-Level Debug"
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default n
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depends on DEBUG
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---help---
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Enable very low-level register access debug. Depends on DEBUG.
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endmenu
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endif
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config LPC43_EVNTMNTR
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bool "Event Monitor"
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default n
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@ -118,6 +118,10 @@ ifeq ($(CONFIG_GPIO_IRQ),y)
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CHIP_CSRCS += lpc43_gpioint.c
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endif
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ifeq ($(CONFIG_LPC43_ETHERNET),y)
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CHIP_CSRCS += lpc43_ethernet.c
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endif
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ifeq ($(CONFIG_LPC43_SPI),y)
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CHIP_CSRCS += lpc43_spi.c
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endif
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@ -181,7 +181,8 @@
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/* MAC frame filter register */
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#define ETH_MACFFLT_PR (1 << 0) /* Bit 0: Promiscuous mode */
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/* Bits 1-2: Reserved */
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#define ETH_MACFFLT_HUC (1 << 1) /* Bit 1: Hash Unicast */
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#define ETH_MACFFLT_HMC (1 << 2) /* Bit 2: Hash Multicast */
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#define ETH_MACFFLT_DAIF (1 << 3) /* Bit 3: Destination address inverse filtering */
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#define ETH_MACFFLT_PM (1 << 4) /* Bit 4: Pass all multicast */
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#define ETH_MACFFLT_DBF (1 << 5) /* Bit 5: Disable Broadcast Frames */
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@ -191,9 +192,9 @@
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# define ETH_MACFFLT_PCF_PAUSE (1 << ETH_MACFFLT_PCF_SHIFT) /* Prevents all except Pause control frames */
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# define ETH_MACFFLT_PCF_ALL (2 << ETH_MACFFLT_PCF_SHIFT) /* Forwards all control frames */
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# define ETH_MACFFLT_PCF_FILTER (3 << ETH_MACFFLT_PCF_SHIFT) /* Forwards all that pass address filter */
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#define ETH_MACFFLT_SAIF (1 << 8) /* Bit 8: Source address inverse filtering */
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#define ETH_MACFFLT_SAF (1 << 9) /* Bit 9: Source address filter */
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/* Bits 10-30: Reserved */
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/* Bit 8-9: Reserved */
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#define ETH_MACFFLT_HPF (1 << 10) /* Bit 10: Hash or perfect filter */
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/* Bits 11-30: Reserved */
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#define ETH_MACFFLT_RA (1 << 31) /* Bit 31: Receive all */
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/* MAC hash table high/low register (32-bit values) */
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@ -208,7 +209,7 @@
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# define ETH_MACMIIA_CR_100_150 (1 << ETH_MACMIIA_CR_SHIFT) /* 100-150 MHz CLK_M4_ETHERNET/62 */
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# define ETH_MACMIIA_CR_20_35 (2 << ETH_MACMIIA_CR_SHIFT) /* 20-35 MHz CLK_M4_ETHERNET/16 */
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# define ETH_MACMIIA_CR_35_60 (3 << ETH_MACMIIA_CR_SHIFT) /* 35-60 MHz CLK_M4_ETHERNET/26 */
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# define ETH_MACMIIA_CR_150_168 (4 << ETH_MACMIIA_CR_SHIFT) /* 150-168 MHz CLK_M4_ETHERNET/102 */
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# define ETH_MACMIIA_CR_150_250 (4 << ETH_MACMIIA_CR_SHIFT) /* 150-250 MHz CLK_M4_ETHERNET/102 */
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# define ETH_MACMIIA_CR_250_300 (5 << ETH_MACMIIA_CR_SHIFT) /* 250-300 MHz CLK_M4_ETHERNET/124 */
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# define ETH_MACMIIA_CR_DIV42 (8 << ETH_MACMIIA_CR_SHIFT) /* 60-100 MHz CLK_M4_ETHERNET/42 */
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# define ETH_MACMIIA_CR_DIV62 (9 << ETH_MACMIIA_CR_SHIFT) /* 100-150 MHz CLK_M4_ETHERNET/62 */
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@ -314,7 +315,7 @@
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/* Bits 4-8: Reserved */
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#define ETH_MACIM_TSIM (1 << 9) /* Bit 9: Time stamp interrupt mask */
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/* Bits 10-31: Reserved */
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#define ETH_MACIM_ALLINTS (ETH_MACIM_PMTIM|ETH_MACIM_TSTIM)
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#define ETH_MACIM_ALLINTS (ETH_MACIM_PMTIM|ETH_MACIM_TSIM)
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/* MAC address 0 high register */
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@ -499,9 +500,9 @@
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#define ETH_TDES0_CC_MASK (15 << ETH_TDES0_CC_SHIFT)
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#define ETH_TDES0_VF (1 << 7) /* Bit 7: VLAN frame */
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#define ETH_TDES0_EC (1 << 8) /* Bit 8: Excessive collision */
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#define ETH_TDES0_LC (1 << 9) /* Bit 9: Late collision */
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#define ETH_TDES0_LCL (1 << 9) /* Bit 9: Late collision */
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#define ETH_TDES0_NC (1 << 10) /* Bit 10: No carrier */
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#define ETH_TDES0_LC (1 << 11) /* Bit 11: Loss of carrier */
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#define ETH_TDES0_LCR (1 << 11) /* Bit 11: Loss of carrier */
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#define ETH_TDES0_IPE (1 << 12) /* Bit 12: IP payload error */
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#define ETH_TDES0_FF (1 << 13) /* Bit 13: Frame flushed */
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#define ETH_TDES0_JT (1 << 14) /* Bit 14: Jabber timeout */
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@ -536,7 +537,7 @@
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#define ETH_RDES0_ESA (1 << 0) /* Bit 0: Extended status available */
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#define ETH_RDES0_CE (1 << 1) /* Bit 1: CRC error */
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#define ETH_RDES0_DE (1 << 2) /* Bit 2: Dribble bit error */
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#define ETH_RDES0_DRE (1 << 2) /* Bit 2: Dribble bit error */
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#define ETH_RDES0_RE (1 << 3) /* Bit 3: Receive error */
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#define ETH_RDES0_RWT (1 << 4) /* Bit 4: Receive watchdog timeout */
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#define ETH_RDES0_FT (1 << 5) /* Bit 5: Frame type */
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@ -548,7 +549,7 @@
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#define ETH_RDES0_OE (1 << 11) /* Bit 11: Overflow error */
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#define ETH_RDES0_LE (1 << 12) /* Bit 12: Length error */
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#define ETH_RDES0_SAF (1 << 13) /* Bit 13: Source address filter fail */
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#define ETH_RDES0_DE (1 << 14) /* Bit 14: Descriptor error */
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#define ETH_RDES0_DS (1 << 14) /* Bit 14: Descriptor error */
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#define ETH_RDES0_ES (1 << 15) /* Bit 15: Error summary */
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#define ETH_RDES0_FL_SHIFT (16) /* Bits 16-29: Frame length */
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#define ETH_RDES0_FL_MASK (0x3fff << ETH_RDES0_FL_SHIFT)
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@ -584,12 +585,12 @@
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* transparent clock) */
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# define ETH_RDES4_MT_PDELREQMM (6 << ETH_RDES4_MT_SHIFT) /* Pdelay_Resp (in peer-to-peer
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* transparent clock) */
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# define ETH_RDES4_MT_PDELREQFUS (7 << ETH_RDES4_MT_SHIFT) /* Pdelay_Resp_Follow_Up (in
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# define ETH_RDES4_MT_PDELRESFUS (7 << ETH_RDES4_MT_SHIFT) /* Pdelay_Resp_Follow_Up (in
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* peer-to-peer transparent clock) */
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# define ETH_RDES4_MT_PDELREQFUS (8 << ETH_RDES4_MT_SHIFT) /* Announce */
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# define ETH_RDES4_MT_PDELREQFUS (9 << ETH_RDES4_MT_SHIFT) /* Management */
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# define ETH_RDES4_MT_PDELREQFUS (10 << ETH_RDES4_MT_SHIFT) /* Signaling */
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# define ETH_RDES4_MT_PDELREQFUS (15 << ETH_RDES4_MT_SHIFT) /* PTP packet with Reserved message type */
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# define ETH_RDES4_MT_ANNOUNCE (8 << ETH_RDES4_MT_SHIFT) /* Announce */
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# define ETH_RDES4_MT_MANAGEMENT (9 << ETH_RDES4_MT_SHIFT) /* Management */
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# define ETH_RDES4_MT_SIGNALING (10 << ETH_RDES4_MT_SHIFT) /* Signaling */
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# define ETH_RDES4_MT_PTP (15 << ETH_RDES4_MT_SHIFT) /* PTP packet with Reserved message type */
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#define ETH_RDES4_PTPTYPE (1 << 12) /* Bit 12: PTP frame type */
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#define ETH_RDES4_PTPVERSION (1 << 13) /* Bit 13: PTP version */
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/* Bits 14-31: Reserved */
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@ -662,6 +663,5 @@ extern "C"
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* LPC43_NETHERNET > 0 */
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#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_ETHERNET_H */
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4008
arch/arm/src/lpc43xx/lpc43_ethernet.c
Normal file
4008
arch/arm/src/lpc43xx/lpc43_ethernet.c
Normal file
File diff suppressed because it is too large
Load Diff
93
arch/arm/src/lpc43xx/lpc43_ethernet.h
Normal file
93
arch/arm/src/lpc43xx/lpc43_ethernet.h
Normal file
@ -0,0 +1,93 @@
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/************************************************************************************
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* arch/arm/src/lpc43xx/lpc43_eth.h
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*
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* Copyright (C) 2009-2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43_ETH_H
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#define __ARCH_ARM_SRC_LPC43XX_LPC43_ETH_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#include "chip/lpc43_ethernet.h"
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#ifndef __ASSEMBLY__
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C" {
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#else
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#define EXTERN extern
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#endif
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/************************************************************************************
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* Function: lpc43_phy_boardinitialize
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*
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* Description:
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* Some boards require specialized initialization of the PHY before it can be used.
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* This may include such things as configuring GPIOs, resetting the PHY, etc. If
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* CONFIG_LPC43_PHYINIT is defined in the configuration then the board specific
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* logic must provide lpc43_phyinitialize(); The LPC43 Ethernet driver will call
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* this function one time before it first uses the PHY.
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*
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* Parameters:
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* intf - Always zero for now.
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*
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* Returned Value:
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* OK on success; Negated errno on failure.
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*
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* Assumptions:
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*
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************************************************************************************/
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#ifdef CONFIG_LPC43_PHYINIT
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int lpc43_phy_boardinitialize(int intf);
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#endif
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#undef EXTERN
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#if defined(__cplusplus)
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_ETH_H */
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