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Fix units used in page table address calculation

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2908 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2010-09-01 21:28:14 +00:00
parent 463eb8bd99
commit ad6b0be05a
2 changed files with 17 additions and 15 deletions
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19
arch/arm/src/arm/pg_macros.h
View File

@ -132,15 +132,6 @@
#define PT_SIZE (4*PTE_NPAGES)
/* Sizes of Memory Regions **************************************************/
#define PG_L2_LOCKED_SIZE (4*CONFIG_PAGING_NLOCKED)
#define PG_L2_PAGED_PSIZE (4*CONFIG_PAGING_NPPAGED)
#define PG_L2_PAGED_VSIZE (4*CONFIG_PAGING_NVPAGED)
#define PG_L2_TEXT_PSIZE (PG_L2_LOCKED_SIZE + PG_L2_PAGED_PSIZE)
#define PG_L2_TEXT_VSIZE (PG_L2_LOCKED_SIZE + PG_L2_PAGED_VSIZE)
#define PG_L2_DATA_SIZE (4*PG_DATA_NPAGES)
/* Virtual Page Table Location **********************************************/
/* Check if the virtual address of the page table has been defined. It should
@ -151,7 +142,7 @@
*/
#ifndef PGTABLE_BASE_VADDR
# define PGTABLE_BASE_VADDR (CONFIG_DRAM_VSTART + PG_L2_TEXT_VSIZE + PG_L2_DATA_SIZE)
# define PGTABLE_BASE_VADDR (PG_LOCKED_VBASE + PG_TEXT_VSIZE + PG_DATA_SIZE)
#endif
/* Addresses of Memory Regions **********************************************/
@ -173,6 +164,7 @@
#define PG_L2_LOCKED_OFFSET (((PG_LOCKED_VBASE & 0x000fffff) >> PAGESHIFT) << 2)
#define PG_L2_LOCKED_PADDR (PGTABLE_L2_BASE_PADDR + PG_L2_LOCKED_OFFSET)
#define PG_L2_LOCKED_VADDR (PGTABLE_L2_BASE_VADDR + PG_L2_LOCKED_OFFSET)
#define PG_L2_LOCKED_SIZE (4*CONFIG_PAGING_NLOCKED)
/* We position the paged region PTEs immediately after the locked
* region PTEs. NOTE that the size of the paged regions is much
@ -185,6 +177,7 @@
#define PG_L2_PAGED_PADDR (PG_L2_LOCKED_PADDR + PG_L2_LOCKED_SIZE)
#define PG_L2_PAGED_VADDR (PG_L2_LOCKED_VADDR + PG_L2_LOCKED_SIZE)
#define PG_L2_PAGED_SIZE (4*CONFIG_PAGING_NVPAGED)
/* This describes the overall text region */
@ -193,14 +186,16 @@
#define PG_L2_TEXT_PADDR PG_L2_LOCKED_PADDR
#define PG_L2_TEXT_VADDR PG_L2_LOCKED_VADDR
#define PG_L2_TEXT_SIZE (PG_L2_LOCKED_SIZE + PG_L2_PAGED_SIZE)
/* We position the data section PTEs just after the text region PTE's */
#define PG_L1_DATA_PADDR (PGTABLE_BASE_PADDR + ((PG_DATA_VBASE >> 20) << 2))
#define PG_L1_DATA_VADDR (PGTABLE_BASE_VADDR + ((PG_DATA_VBASE >> 20) << 2))
#define PG_L2_DATA_PADDR (PG_L2_LOCKED_PADDR + PG_L2_TEXT_PSIZE)
#define PG_L2_DATA_VADDR (PG_L2_LOCKED_VADDR + PG_L2_TEXT_VSIZE)
#define PG_L2_DATA_PADDR (PG_L2_LOCKED_PADDR + PG_L2_TEXT_SIZE)
#define PG_L2_DATA_VADDR (PG_L2_LOCKED_VADDR + PG_L2_TEXT_SIZE)
#define PG_L2_DATA_SIZE (4*PG_DATA_NPAGES)
/* Page Table Info **********************************************************/

13
configs/ea3131/README.txt
View File

@ -361,10 +361,17 @@ On-Demand Paging
...
The locked region is initially unmapped. But the data region and page table
regions must be mapped in a similar manner.
regions must be mapped in a similar manner. Those
data offset = ((0x00094000 >> 10) << 2) = 0x00000940
L1 offset = ((0x0009c000 >> 10) << 2) = 0x000009c0
Data:
Virtual address = 0x11094000 Offset = 0x00064000
Physical address = 0x1104c000
L2 offset = ((0x00094000 >> 10) << 2) = 0x00000940
Page table:
Virtual address = 0x1109c000 Offset = 0x0009c000
Physical address = 0x11054000
L2 offset = ((0x0009c000 >> 10) << 2) = 0x000009c0
Build Sequence:
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