configs/metro-m4: Fix RxD interrupt pin selection. The number SERCOM interrupts do not refer to PAD numbers, but to bit positions in the INFLAG register (very tiny footnote in the data sheet). With with final fix, the basic NSH configuration appears fully functional.
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Gregory Nutt
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aee1c39eab
@ -86,8 +86,8 @@
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#define SAM_IRQ_EXTINT14 (SAM_IRQ_EXTINT + 26) /* 26 EIC: EXTINT14 */
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#define SAM_IRQ_EXTINT15 (SAM_IRQ_EXTINT + 27) /* 27 EIC: EXTINT15 */
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#define SAM_IRQ_FREQM (SAM_IRQ_EXTINT + 28) /* 28 FREQM: Done */
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#define SAM_IRQ_NVMCTRL0 (SAM_IRQ_EXTINT + 29) /* 29 NVMCTRL: 0-7 */
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#define SAM_IRQ_NVMCTRL1 (SAM_IRQ_EXTINT + 30) /* 30 NVMCTRL: 8-10 */
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#define SAM_IRQ_NVMCTRL0 (SAM_IRQ_EXTINT + 29) /* 29 NVMCTRL: INTFLAG[0-7] */
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#define SAM_IRQ_NVMCTRL1 (SAM_IRQ_EXTINT + 30) /* 30 NVMCTRL: INTFLAG[8-10] */
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#define SAM_IRQ_DMACH0 (SAM_IRQ_EXTINT + 31) /* 31 DMA Channel 0: SUSP, TCMPL, TERR */
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#define SAM_IRQ_DMACH1 (SAM_IRQ_EXTINT + 32) /* 32 DMA Channel 1: SUSP, TCMPL, TERR */
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#define SAM_IRQ_DMACH2 (SAM_IRQ_EXTINT + 33) /* 33 DMA Channel 2: SUSP, TCMPL, TERR */
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@ -100,38 +100,38 @@
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#define SAM_IRQ_EVSYS4_11 (SAM_IRQ_EXTINT + 40) /* 40 EVSYS Channels 4-11: EVD, OVR */
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#define SAM_IRQ_PAC (SAM_IRQ_EXTINT + 41) /* 41 PAC: ERR */
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#define SAM_IRQ_RAMECC (SAM_IRQ_EXTINT + 45) /* 45 RAM ECC: 0-1 */
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#define SAM_IRQ_SERCOM0_0 (SAM_IRQ_EXTINT + 46) /* 46 SERCOM0: 0 */
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#define SAM_IRQ_SERCOM0_1 (SAM_IRQ_EXTINT + 47) /* 47 SERCOM0: 1 */
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#define SAM_IRQ_SERCOM0_2 (SAM_IRQ_EXTINT + 48) /* 48 SERCOM0: 2 */
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#define SAM_IRQ_SERCOM0_46 (SAM_IRQ_EXTINT + 49) /* 49 SERCOM0: 4-6 */
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#define SAM_IRQ_SERCOM1_0 (SAM_IRQ_EXTINT + 50) /* 50 SERCOM1: 0 */
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#define SAM_IRQ_SERCOM1_1 (SAM_IRQ_EXTINT + 51) /* 51 SERCOM1: 1 */
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#define SAM_IRQ_SERCOM1_2 (SAM_IRQ_EXTINT + 52) /* 52 SERCOM1: 2 */
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#define SAM_IRQ_SERCOM1_46 (SAM_IRQ_EXTINT + 53) /* 53 SERCOM1: 4-6 */
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#define SAM_IRQ_SERCOM2_0 (SAM_IRQ_EXTINT + 54) /* 54 SERCOM2: 0 */
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#define SAM_IRQ_SERCOM2_1 (SAM_IRQ_EXTINT + 55) /* 55 SERCOM2: 1 */
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#define SAM_IRQ_SERCOM2_2 (SAM_IRQ_EXTINT + 56) /* 56 SERCOM2: 2 */
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#define SAM_IRQ_SERCOM2_46 (SAM_IRQ_EXTINT + 57) /* 57 SERCOM2: 4-6 */
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#define SAM_IRQ_SERCOM3_0 (SAM_IRQ_EXTINT + 58) /* 58 SERCOM3: 0 */
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#define SAM_IRQ_SERCOM3_1 (SAM_IRQ_EXTINT + 59) /* 59 SERCOM3: 1 */
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#define SAM_IRQ_SERCOM3_2 (SAM_IRQ_EXTINT + 60) /* 60 SERCOM3: 2 */
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#define SAM_IRQ_SERCOM3_46 (SAM_IRQ_EXTINT + 61) /* 61 SERCOM3: 4-6 */
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#define SAM_IRQ_SERCOM4_0 (SAM_IRQ_EXTINT + 62) /* 62 SERCOM4: 0 */
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#define SAM_IRQ_SERCOM4_1 (SAM_IRQ_EXTINT + 63) /* 63 SERCOM4: 1 */
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#define SAM_IRQ_SERCOM4_2 (SAM_IRQ_EXTINT + 64) /* 64 SERCOM4: 2 */
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#define SAM_IRQ_SERCOM4_46 (SAM_IRQ_EXTINT + 65) /* 65 SERCOM4: 4-6 */
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#define SAM_IRQ_SERCOM5_0 (SAM_IRQ_EXTINT + 66) /* 66 SERCOM5: 0 */
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#define SAM_IRQ_SERCOM5_1 (SAM_IRQ_EXTINT + 67) /* 67 SERCOM5: 1 */
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#define SAM_IRQ_SERCOM5_2 (SAM_IRQ_EXTINT + 68) /* 68 SERCOM5: 2 */
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#define SAM_IRQ_SERCOM5_46 (SAM_IRQ_EXTINT + 69) /* 69 SERCOM5: 4-6 */
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#define SAM_IRQ_SERCOM6_0 (SAM_IRQ_EXTINT + 70) /* 70 SERCOM6: 0 */
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#define SAM_IRQ_SERCOM6_1 (SAM_IRQ_EXTINT + 71) /* 71 SERCOM6: 1 */
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#define SAM_IRQ_SERCOM6_2 (SAM_IRQ_EXTINT + 72) /* 72 SERCOM6: 2 */
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#define SAM_IRQ_SERCOM6_46 (SAM_IRQ_EXTINT + 73) /* 73 SERCOM6: 4-6 */
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#define SAM_IRQ_SERCOM7_0 (SAM_IRQ_EXTINT + 74) /* 74 SERCOM7: 0 */
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#define SAM_IRQ_SERCOM7_1 (SAM_IRQ_EXTINT + 75) /* 75 SERCOM7: 1 */
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#define SAM_IRQ_SERCOM7_2 (SAM_IRQ_EXTINT + 76) /* 76 SERCOM7: 2 */
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#define SAM_IRQ_SERCOM7_46 (SAM_IRQ_EXTINT + 77) /* 77 SERCOM7: 4-6 */
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#define SAM_IRQ_SERCOM0_0 (SAM_IRQ_EXTINT + 46) /* 46 SERCOM0: INTFLAG[0] */
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#define SAM_IRQ_SERCOM0_1 (SAM_IRQ_EXTINT + 47) /* 47 SERCOM0: INTFLAG[1] */
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#define SAM_IRQ_SERCOM0_2 (SAM_IRQ_EXTINT + 48) /* 48 SERCOM0: INTFLAG[2] */
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#define SAM_IRQ_SERCOM0_46 (SAM_IRQ_EXTINT + 49) /* 49 SERCOM0: INTFLAG[3-6] */
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#define SAM_IRQ_SERCOM1_0 (SAM_IRQ_EXTINT + 50) /* 50 SERCOM1: INTFLAG[0] */
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#define SAM_IRQ_SERCOM1_1 (SAM_IRQ_EXTINT + 51) /* 51 SERCOM1: INTFLAG[1] */
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#define SAM_IRQ_SERCOM1_2 (SAM_IRQ_EXTINT + 52) /* 52 SERCOM1: INTFLAG[2] */
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#define SAM_IRQ_SERCOM1_46 (SAM_IRQ_EXTINT + 53) /* 53 SERCOM1: INTFLAG[3-6] */
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#define SAM_IRQ_SERCOM2_0 (SAM_IRQ_EXTINT + 54) /* 54 SERCOM2: INTFLAG[0] */
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#define SAM_IRQ_SERCOM2_1 (SAM_IRQ_EXTINT + 55) /* 55 SERCOM2: INTFLAG[1] */
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#define SAM_IRQ_SERCOM2_2 (SAM_IRQ_EXTINT + 56) /* 56 SERCOM2: INTFLAG[2] */
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#define SAM_IRQ_SERCOM2_46 (SAM_IRQ_EXTINT + 57) /* 57 SERCOM2: INTFLAG[3-6] */
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#define SAM_IRQ_SERCOM3_0 (SAM_IRQ_EXTINT + 58) /* 58 SERCOM3: INTFLAG[0] */
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#define SAM_IRQ_SERCOM3_1 (SAM_IRQ_EXTINT + 59) /* 59 SERCOM3: INTFLAG[1] */
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#define SAM_IRQ_SERCOM3_2 (SAM_IRQ_EXTINT + 60) /* 60 SERCOM3: INTFLAG[2] */
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#define SAM_IRQ_SERCOM3_46 (SAM_IRQ_EXTINT + 61) /* 61 SERCOM3: INTFLAG[3-6] */
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#define SAM_IRQ_SERCOM4_0 (SAM_IRQ_EXTINT + 62) /* 62 SERCOM4: INTFLAG[0] */
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#define SAM_IRQ_SERCOM4_1 (SAM_IRQ_EXTINT + 63) /* 63 SERCOM4: INTFLAG[1] */
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#define SAM_IRQ_SERCOM4_2 (SAM_IRQ_EXTINT + 64) /* 64 SERCOM4: INTFLAG[2] */
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#define SAM_IRQ_SERCOM4_46 (SAM_IRQ_EXTINT + 65) /* 65 SERCOM4: INTFLAG[3-6] */
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#define SAM_IRQ_SERCOM5_0 (SAM_IRQ_EXTINT + 66) /* 66 SERCOM5: INTFLAG[0] */
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#define SAM_IRQ_SERCOM5_1 (SAM_IRQ_EXTINT + 67) /* 67 SERCOM5: INTFLAG[1] */
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#define SAM_IRQ_SERCOM5_2 (SAM_IRQ_EXTINT + 68) /* 68 SERCOM5: INTFLAG[2] */
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#define SAM_IRQ_SERCOM5_46 (SAM_IRQ_EXTINT + 69) /* 69 SERCOM5: INTFLAG[3-6] */
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#define SAM_IRQ_SERCOM6_0 (SAM_IRQ_EXTINT + 70) /* 70 SERCOM6: INTFLAG[0] */
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#define SAM_IRQ_SERCOM6_1 (SAM_IRQ_EXTINT + 71) /* 71 SERCOM6: INTFLAG[1] */
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#define SAM_IRQ_SERCOM6_2 (SAM_IRQ_EXTINT + 72) /* 72 SERCOM6: INTFLAG[2] */
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#define SAM_IRQ_SERCOM6_46 (SAM_IRQ_EXTINT + 73) /* 73 SERCOM6: INTFLAG[3-6] */
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#define SAM_IRQ_SERCOM7_0 (SAM_IRQ_EXTINT + 74) /* 74 SERCOM7: INTFLAG[0] */
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#define SAM_IRQ_SERCOM7_1 (SAM_IRQ_EXTINT + 75) /* 75 SERCOM7: INTFLAG[1] */
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#define SAM_IRQ_SERCOM7_2 (SAM_IRQ_EXTINT + 76) /* 76 SERCOM7: INTFLAG[2] */
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#define SAM_IRQ_SERCOM7_46 (SAM_IRQ_EXTINT + 77) /* 77 SERCOM7: INTFLAG[3-6] */
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#define SAM_IRQ_CAN0 (SAM_IRQ_EXTINT + 78) /* 78 CAN0: Line0, Line1 */
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#define SAM_IRQ_CAN1 (SAM_IRQ_EXTINT + 79) /* 79 CAN1: Line0, Line1 */
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#define SAM_IRQ_USB (SAM_IRQ_EXTINT + 80) /* 80 USB: EORSM, DNRSM, EORST RST,
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@ -99,16 +99,28 @@ STATUS
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+#define BOARD_GCLK3_SOURCE 4 /* Select OSCULP32K as GCLK3 source */
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With that workaround, the port gets past all clock and USART
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configuration and, in fact, completely through OS initialization and
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application startup! The NSH shell runs and the NSH prompt is presented
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on the serial console at the correct baud. Serial input, however, is
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not received. There are no serial Rx interrupts! So there is still
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more to be done.
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configuration. A new configuration option was added,
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CONFIG_METRO_M4_32KHZXTAL. By default this workaround is in place.
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But you can enable CONFIG_METRO_M4_32KHZXTAL if you want to further
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study the XOSC32K problem.
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A new configuration option was added, CONFIG_METRO_M4_32KHZXTAL. By
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default this workaround is in place. But you can enabled
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CONFIG_METRO_M4_32KHZXTAL if you want to further study the XOSC32K
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problem.
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With that workaround (and a bunch of other fixes), the basic NSH
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configuration appears fully function, indicating the the board bring-
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up is complete:
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NuttShell (NSH) NuttX-7.25
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nsh> help
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help usage: help [-v] [<cmd>]
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[ cmp false mkdir set uname
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? dirname help mh sh usleep
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basename dd hexdump mv sleep xd
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break echo kill mw test
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cat exec ls rm time
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cp exit mb rmdir true
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Builtin Apps:
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nsh>
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Unlocking FLASH
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===============
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@ -445,8 +445,8 @@
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#define BOARD_SERCOM3_PINMAP_PAD2 0 /* PAD2: (not used) */
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#define BOARD_SERCOM3_PINMAP_PAD3 0 /* PAD3: (not used) */
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#define BOARD_TXIRQ_SERCOM3 SAM_IRQ_SERCOM3_0 /* PAD0 */
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#define BOARD_RXIRQ_SERCOM3 SAM_IRQ_SERCOM3_1 /* PAD1 */
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#define BOARD_TXIRQ_SERCOM3 SAM_IRQ_SERCOM3_0 /* INTFLAG[0] DRE */
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#define BOARD_RXIRQ_SERCOM3 SAM_IRQ_SERCOM3_2 /* INTFLAG[2] RXC */
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#define BOARD_SERCOM3_COREGEN 1 /* 48MHz Core clock */
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#define BOARD_SERCOM3_CORELOCK FALSE /* Don't lock the CORECLOCK */
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