SAMV7 MCAN: Update some register debug output
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d53f6b9353
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@ -688,11 +688,9 @@ struct sam_mcan_s
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static uint32_t mcan_getreg(FAR struct sam_mcan_s *priv, int offset);
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static uint32_t mcan_getreg(FAR struct sam_mcan_s *priv, int offset);
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static void mcan_putreg(FAR struct sam_mcan_s *priv, int offset, uint32_t regval);
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static void mcan_putreg(FAR struct sam_mcan_s *priv, int offset, uint32_t regval);
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#ifdef CONFIG_SAMV7_MCAN_REGDEBUG
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#ifdef CONFIG_SAMV7_MCAN_REGDEBUG
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static void mcan_dumpctrlregs(FAR struct sam_mcan_s *priv, FAR const char *msg);
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static void mcan_dumpregs(FAR struct sam_mcan_s *priv, FAR const char *msg);
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static void mcan_dumpmbregs(FAR struct sam_mcan_s *priv, FAR const char *msg);
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#else
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#else
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# define mcan_dumpctrlregs(priv,msg)
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# define mcan_dumpregs(priv,msg)
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# define mcan_dumpmbregs(priv,msg)
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#endif
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#endif
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/* Semaphore helpers */
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/* Semaphore helpers */
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@ -1016,7 +1014,7 @@ static void mcan_putreg(FAR struct sam_mcan_s *priv, int offset, uint32_t regval
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#endif
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#endif
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/****************************************************************************
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/****************************************************************************
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* Name: mcan_dumpctrlregs
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* Name: mcan_dumpregs
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*
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*
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* Description:
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* Description:
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* Dump the contents of all CAN control registers
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* Dump the contents of all CAN control registers
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@ -1030,86 +1028,79 @@ static void mcan_putreg(FAR struct sam_mcan_s *priv, int offset, uint32_t regval
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****************************************************************************/
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****************************************************************************/
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#ifdef CONFIG_SAMV7_MCAN_REGDEBUG
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#ifdef CONFIG_SAMV7_MCAN_REGDEBUG
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static void mcan_dumpctrlregs(FAR struct sam_mcan_s *priv, FAR const char *msg)
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static void mcan_dumpregs(FAR struct sam_mcan_s *priv, FAR const char *msg)
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{
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{
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FAR const struct sam_config_s *config = priv->config;
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FAR const struct sam_config_s *config = priv->config;
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unsigned long addr;
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if (msg)
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lldbg("MCAN%d Registers: %s\n", config->port, msg);
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{
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lldbg(" Base: %08x\n", config->base);
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canlldbg("Control Registers: %s\n", msg);
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}
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else
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{
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canlldbg("Control Registers:\n");
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}
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/* CAN control and status registers */
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lldbg(" CUST: %08x FBTP: %08x TEST: %08x RWD: %08x\n",
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getreg32(config->base + SAM_MCAN_CUST_OFFSET),
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getreg32(config->base + SAM_MCAN_FBTP_OFFSET),
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getreg32(config->base + SAM_MCAN_TEST_OFFSET),
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getreg32(config->base + SAM_MCAN_RWD_OFFSET));
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lldbg(" MR: %08x IMR: %08x SR: %08x\n",
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lldbg(" CCCR: %08x BTP: %08x TSCC: %08x TSCV: %08x\n",
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getreg32(config->base + SAM_CAN_MR_OFFSET),
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getreg32(config->base + SAM_MCAN_CCCR_OFFSET),
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getreg32(config->base + SAM_CAN_IMR_OFFSET),
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getreg32(config->base + SAM_MCAN_BTP_OFFSET),
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getreg32(config->base + SAM_CAN_SR_OFFSET));
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getreg32(config->base + SAM_MCAN_TSCC_OFFSET),
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getreg32(config->base + SAM_MCAN_TSCV_OFFSET));
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lldbg(" BR: %08x TIM: %08x TIMESTP: %08x\n",
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lldbg(" TOCC: %08x TOCV: %08x ECR: %08x PSR: %08x\n",
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getreg32(config->base + SAM_CAN_BR_OFFSET),
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getreg32(config->base + SAM_MCAN_TOCC_OFFSET),
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getreg32(config->base + SAM_CAN_TIM_OFFSET),
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getreg32(config->base + SAM_MCAN_TOCV_OFFSET),
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getreg32(config->base + SAM_CAN_TIMESTP_OFFSET));
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getreg32(config->base + SAM_MCAN_ECR_OFFSET),
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getreg32(config->base + SAM_MCAN_PSR_OFFSET));
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lldbg(" ECR: %08x WPMR: %08x WPSR: %08x\n",
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lldbg(" IR: %08x IE: %08x ILS: %08x ILE: %08x\n",
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getreg32(config->base + SAM_CAN_ECR_OFFSET),
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getreg32(config->base + SAM_MCAN_IR_OFFSET),
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getreg32(config->base + SAM_CAN_TCR_OFFSET),
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getreg32(config->base + SAM_MCAN_IE_OFFSET),
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getreg32(config->base + SAM_CAN_ACR_OFFSET));
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getreg32(config->base + SAM_MCAN_ILS_OFFSET),
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}
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getreg32(config->base + SAM_MCAN_ILE_OFFSET));
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#endif
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/****************************************************************************
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lldbg(" GFC: %08x SIDFC: %08x XIDFC: %08x XIDAM: %08x\n",
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* Name: mcan_dumpmbregs
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getreg32(config->base + SAM_MCAN_GFC_OFFSET),
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*
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getreg32(config->base + SAM_MCAN_SIDFC_OFFSET),
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* Description:
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getreg32(config->base + SAM_MCAN_XIDFC_OFFSET),
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* Dump the contents of all CAN mailbox registers
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getreg32(config->base + SAM_MCAN_XIDAM_OFFSET));
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*
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* Input Parameters:
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* priv - A reference to the CAN peripheral state
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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#ifdef CONFIG_SAMV7_MCAN_REGDEBUG
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lldbg(" HPMS: %08x NDAT1: %08x NDAT2: %08x RXF0C: %08x\n",
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static void mcan_dumpmbregs(FAR struct sam_mcan_s *priv, FAR const char *msg)
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getreg32(config->base + SAM_MCAN_HPMS_OFFSET),
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{
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getreg32(config->base + SAM_MCAN_NDAT1_OFFSET),
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FAR const struct sam_config_s *config = priv->config;
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getreg32(config->base + SAM_MCAN_NDAT2_OFFSET),
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uintptr_t mbbase;
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getreg32(config->base + SAM_MCAN_RXF0C_OFFSET));
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int i;
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if (msg)
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lldbg(" RXF0S: %08x FXF0A: %08x RXBC: %08x RXF1C: %08x\n",
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{
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getreg32(config->base + SAM_MCAN_RXF0S_OFFSET),
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canlldbg("Mailbox Registers: %s\n", msg);
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getreg32(config->base + SAM_MCAN_RXF0A_OFFSET),
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}
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getreg32(config->base + SAM_MCAN_RXBC_OFFSET),
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else
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getreg32(config->base + SAM_MCAN_RXF1C_OFFSET));
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{
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canlldbg("Mailbox Registers:\n");
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}
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for (i = 0; i < SAM_CAN_NMAILBOXES; i++)
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lldbg(" RXF1S: %08x FXF1A: %08x RXESC: %08x TXBC: %08x\n",
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{
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getreg32(config->base + SAM_MCAN_RXF1S_OFFSET),
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mbbase = config->base + SAM_CAN_MBn_OFFSET(i);
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getreg32(config->base + SAM_MCAN_RXF1A_OFFSET),
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lldbg(" MB%d:\n", i);
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getreg32(config->base + SAM_MCAN_RXESC_OFFSET),
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getreg32(config->base + SAM_MCAN_TXBC_OFFSET));
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/* CAN mailbox registers */
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lldbg(" TXFQS: %08x TXESC: %08x TXBRP: %08x TXBAR: %08x\n",
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getreg32(config->base + SAM_MCAN_TXFQS_OFFSET),
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getreg32(config->base + SAM_MCAN_TXESC_OFFSET),
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getreg32(config->base + SAM_MCAN_TXBRP_OFFSET),
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getreg32(config->base + SAM_MCAN_TXBAR_OFFSET));
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lldbg(" MMR: %08x MAM: %08x MID: %08x MFID: %08x\n",
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lldbg(" TXBCR: %08x TXBTO: %08x TXBCF: %08x TXBTIE: %08x\n",
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getreg32(mbbase + SAM_CAN_MMR_OFFSET),
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getreg32(config->base + SAM_MCAN_TXBCR_OFFSET),
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getreg32(mbbase + SAM_CAN_MAM_OFFSET),
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getreg32(config->base + SAM_MCAN_TXBTO_OFFSET),
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getreg32(mbbase + SAM_CAN_MID_OFFSET),
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getreg32(config->base + SAM_MCAN_TXBCF_OFFSET),
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getreg32(mbbase + SAM_CAN_MFID_OFFSET));
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getreg32(config->base + SAM_MCAN_TXBTIE_OFFSET));
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lldbg(" MSR: %08x MDL: %08x MDH: %08x\n",
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lldbg("TXBCIE: %08x TXEFC: %08x TXEFS: %08x TXEFA: %08x\n",
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getreg32(mbbase + SAM_CAN_MSR_OFFSET),
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getreg32(config->base + SAM_MCAN_TXBCIE_OFFSET),
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getreg32(mbbase + SAM_CAN_MDL_OFFSET),
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getreg32(config->base + SAM_MCAN_TXEFC_OFFSET),
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getreg32(mbbase + SAM_CAN_MDH_OFFSET));
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getreg32(config->base + SAM_MCAN_TXEFS_OFFSET),
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}
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getreg32(config->base + SAM_MCAN_TXEFA_OFFSET));
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}
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}
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#endif
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#endif
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@ -1414,8 +1405,7 @@ static int mcan_setup(FAR struct can_dev_s *dev)
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return ret;
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return ret;
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}
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}
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mcan_dumpctrlregs(priv, "After hardware initialization");
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mcan_dumpregs(priv, "After hardware initialization");
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mcan_dumpmbregs(priv, NULL);
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/* Attach the CAN interrupt handler */
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/* Attach the CAN interrupt handler */
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@ -1441,8 +1431,7 @@ static int mcan_setup(FAR struct can_dev_s *dev)
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mcan_putreg(priv, SAM_CAN_IER_OFFSET, CAN_DEBUG_INTS);
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mcan_putreg(priv, SAM_CAN_IER_OFFSET, CAN_DEBUG_INTS);
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#endif
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#endif
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mcan_dumpctrlregs(priv, "After receive setup");
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mcan_dumpregs(priv, "After receive setup");
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mcan_dumpmbregs(priv, NULL);
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/* Enable the interrupts at the NVIC (they are still disabled at the MCAN
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/* Enable the interrupts at the NVIC (they are still disabled at the MCAN
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* peripheral). */
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* peripheral). */
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@ -1740,7 +1729,6 @@ static int mcan_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
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mcan_putreg(priv, SAM_CAN_IER_OFFSET, CAN_INT_MB(mbndx));
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mcan_putreg(priv, SAM_CAN_IER_OFFSET, CAN_INT_MB(mbndx));
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}
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}
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mcan_dumpmbregs(priv, "After send");
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mcan_semgive(priv);
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mcan_semgive(priv);
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return OK;
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return OK;
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}
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}
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