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SAMV7: Apparently the data sheet is wrong, SDRAM clocking must be enabled at the PMC or the SDRAM does not work! The data sheet says that there is no clock control for SDRAMC

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This commit is contained in:
Gregory Nutt 2015-04-04 19:04:29 -06:00
parent b689d8a736
commit c1886c6181
1 changed files with 2 additions and 2 deletions
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4
arch/arm/src/samv7/samv71_periphclks.h
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@ -118,7 +118,7 @@
#define sam_isi_enableclk() sam_enableperiph1(SAM_PID_ISI)
#define sam_pwm1_enableclk() sam_enableperiph1(SAM_PID_PWM1)
#define sam_fpu_enableclk()
#define sam_sdramc_enableclk()
#define sam_sdramc_enableclk() sam_enableperiph1(SAM_PID_SDRAMC)
#define sam_wdt1_enableclk()
#define sam_ccw_enableclk()
@ -186,7 +186,7 @@
#define sam_isi_disableclk() sam_disableperiph1(SAM_PID_ISI)
#define sam_pwm1_disableclk() sam_disableperiph1(SAM_PID_PWM1)
#define sam_fpu_disableclk()
#define sam_sdramc_disableclk()
#define sam_sdramc_disableclk() sam_disableperiph1(SAM_PID_SDRAMC)
#define sam_wdt1_disableclk()
#define sam_ccw_disableclk()