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SAML21 clock config: Fix a misthink in last commit. Move setting of ONDEMAND to after clock is enabled in most cases

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This commit is contained in:
Gregory Nutt 2015-05-21 16:50:55 -06:00
parent b6091c7d83
commit c5f5628875
1 changed files with 6 additions and 6 deletions
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12
configs/saml21-xplained/include/board.h
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@ -192,7 +192,7 @@
* BOARD_DFLL48M_FINEVALUE - Value
*
* Closed loop mode only:
* BOARD_DFLL48M_REFCLK_CLKGEN - See GCLK_PCHCTRL_GEN* definitions
* BOARD_DFLL48M_REFCLK_CLKGEN - GCLK index in the range {0..8}
* BOARD_DFLL48M_MULTIPLIER - Value
* BOARD_DFLL48M_MAXCOARSESTEP - Value
* BOARD_DFLL48M_MAXFINESTEP - Value
@ -215,7 +215,7 @@
/* DFLL closed loop mode configuration */
#define BOARD_DFLL48M_REFCLK_CLKGEN GCLK_PCHCTRL_GEN1
#define BOARD_DFLL48M_REFCLK_CLKGEN 1
#define BOARD_DFLL48M_MULTIPLIER 12
#define BOARD_DFLL48M_QUICKLOCK 1
#define BOARD_DFLL48M_TRACKAFTERFINELOCK 1
@ -236,10 +236,10 @@
* BOARD_FDPLL96M_LPEN - Boolean (defined / not defined)
* BOARD_FDPLL96M_FILTER - See OSCCTRL_DPLLCTRLB_FILTER_* definitions
* BOARD_FDPLL96M_REFCLK - See OSCCTRL_DPLLCTRLB_REFLCK_* definitions
* BOARD_FDPLL96M_REFCLK_CLKGEN - See GCLK_PCHCTRL_GEN* definitions
* BOARD_FDPLL96M_REFCLK_CLKGEN - GCLK index in the range {0..8}
* BOARD_FDPLL96M_LOCKTIME_ENABLE - Boolean (defined / not defined)
* BOARD_FDPLL96M_LOCKTIME - See OSCCTRL_DPLLCTRLB_LTIME_* definitions
* BOARD_FDPLL96M_LOCKTIME_CLKGEN - See GCLK_PCHCTRL_GEN* definitions
* BOARD_FDPLL96M_LOCKTIME_CLKGEN - GCLK index in the range {0..8}
* BOARD_FDPLL96M_REFDIV - Numeric value, 1 - 2047
* BOARD_FDPLL96M_PRESCALER - See OSCCTRL_DPLLPRESC_* definitions
* BOARD_FDPLL96M_REFFREQ - Numeric value
@ -254,10 +254,10 @@
#undef BOARD_FDPLL96M_LPEN
#define BOARD_FDPLL96M_FILTER OSCCTRL_DPLLCTRLB_FILTER_DEFAULT
#define BOARD_FDPLL96M_REFCLK OSCCTRL_DPLLCTRLB_REFLCK_XOSCK32K
#define BOARD_FDPLL96M_REFCLK_CLKGEN GCLK_PCHCTRL_GEN1
#define BOARD_FDPLL96M_REFCLK_CLKGEN 1
#undef BOARD_FDPLL96M_LOCKTIME_ENABLE
#define BOARD_FDPLL96M_LOCKTIME OSCCTRL_DPLLCTRLB_LTIME_NONE
#define BOARD_FDPLL96M_LOCKTIME_CLKGEN GCLK_PCHCTRL_GEN1
#define BOARD_FDPLL96M_LOCKTIME_CLKGEN 1
#define BOARD_FDPLL96M_REFDIV 1
#define BOARD_FDPLL96M_PRESCALER OSCCTRL_DPLLPRESC_DIV1