SAM4E: Various bring-up fixes. NSH now works
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3bb6c2fd57
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ce82132ef1
@ -139,6 +139,7 @@ static inline void sam_supcsetup(void)
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if ((getreg32(SAM_SUPC_SR) & SUPC_SR_OSCSEL) == 0)
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if ((getreg32(SAM_SUPC_SR) & SUPC_SR_OSCSEL) == 0)
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{
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{
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uint32_t delay;
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uint32_t delay;
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putreg32((SUPC_CR_XTALSEL|SUPR_CR_KEY), SAM_SUPC_CR);
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putreg32((SUPC_CR_XTALSEL|SUPR_CR_KEY), SAM_SUPC_CR);
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for (delay = 0;
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for (delay = 0;
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(getreg32(SAM_SUPC_SR) & SUPC_SR_OSCSEL) == 0 && delay < UINT32_MAX;
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(getreg32(SAM_SUPC_SR) & SUPC_SR_OSCSEL) == 0 && delay < UINT32_MAX;
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@ -150,7 +151,7 @@ static inline void sam_supcsetup(void)
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* Name: sam_pmcwait
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* Name: sam_pmcwait
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*
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*
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* Description:
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* Description:
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* Wait for the specide PMC status bit to become "1"
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* Wait for the specified PMC status bit to become "1"
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*
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*
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****************************************************************************/
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****************************************************************************/
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@ -215,7 +216,7 @@ static inline void sam_pmcsetup(void)
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* established.
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* established.
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*/
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*/
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regval = getreg32(SAM_PMC_MCKR);
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regval = getreg32(SAM_PMC_MCKR);
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regval &= ~PMC_MCKR_CSS_MASK;
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regval &= ~PMC_MCKR_CSS_MASK;
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regval |= PMC_MCKR_CSS_MAIN;
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regval |= PMC_MCKR_CSS_MAIN;
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putreg32(regval, SAM_PMC_MCKR);
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putreg32(regval, SAM_PMC_MCKR);
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@ -228,7 +229,7 @@ static inline void sam_pmcsetup(void)
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* to PLLA_MMAX.
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* to PLLA_MMAX.
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*/
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*/
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putreg32(PMC_PMMR_MASK, SAM_PMC_PMMR);
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//putreg32(PMC_PMMR_MASK, SAM_PMC_PMMR);
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#endif
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#endif
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/* Setup PLLA and wait for LOCKA */
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/* Setup PLLA and wait for LOCKA */
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@ -349,4 +350,3 @@ void sam_clockconfig(void)
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sam_enabledefaultmaster();
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sam_enabledefaultmaster();
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}
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}
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@ -739,8 +739,13 @@ static int up_setup(struct uart_dev_s *dev)
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up_serialout(priv, SAM_UART_MR_OFFSET, regval);
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up_serialout(priv, SAM_UART_MR_OFFSET, regval);
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/* Configure the console baud. NOTE: Oversampling by 8 is not supported.
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/* Configure the console baud:
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* This may limit BAUD rates for lower USART clocks.
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*
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* Fbaud = USART_CLOCK / (16 * divisor)
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* divisor = USART_CLOCK / (16 * Fbaud)
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*
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* NOTE: Oversampling by 8 is not supported. This may limit BAUD rates
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* for lower USART clocks.
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*/
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*/
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regval = (SAM_USART_CLOCK + (priv->baud << 3))/(priv->baud << 4);
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regval = (SAM_USART_CLOCK + (priv->baud << 3))/(priv->baud << 4);
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@ -15,6 +15,8 @@ Contents
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- NuttX OABI "buildroot" Toolchain
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- NuttX OABI "buildroot" Toolchain
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- NXFLAT Toolchain
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- NXFLAT Toolchain
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- Atmel Studio 6.1
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- Atmel Studio 6.1
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- Loading Code with J-Link
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- Writing to FLASH using SAM-BA
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- LEDs
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- LEDs
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- Serial Console
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- Serial Console
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- SAM4E-EK-specific Configuration Options
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- SAM4E-EK-specific Configuration Options
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@ -224,22 +226,74 @@ Atmel Studio 6.1
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- Debugging the NuttX Object File:
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- Debugging the NuttX Object File:
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1) Rename object file from nutt to nuttx.elf. That is an extension that
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1) Rename object file from nutt to nuttx.elf. That is an extension that
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will be recognized by the file menu.
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will be recognized by the file menu.
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2) Select the project name, the full path to the NuttX object (called
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2) Select the project name, the full path to the NuttX object (called
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just nuttx with no extension), and chip. Take the time to resolve
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just nuttx with no extension), and chip. Take the time to resolve
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all of the source file linkages or else you will not have source
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all of the source file linkages or else you will not have source
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level debug!
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level debug!
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File menu: File -> Open -> Open object file for debugging
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File menu: File -> Open -> Open object file for debugging
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- Select nuttx.elf object file
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- Select nuttx.elf object file
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- Select AT91SAM4E16
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- Select AT91SAM4E16
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- Select files for symbols as desired
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- Select files for symbols as desired
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- Select debugger
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- Select debugger
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3) Debug menu: Debug -> Start debugging and break
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3) Debug menu: Debug -> Start debugging and break
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- This will reload the nuttx.elf file into FLASH
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- This will reload the nuttx.elf file into FLASH
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STATUS: At this point, Atmel Studio 6.1 claims that my object files are
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not readable. A little more needs to be done to wring out this procedure.
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Loading Code into SRAM with J-Link
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Loading code with the Segger tools and GDB
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------------------------------------------
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1) Change directories into the directory where you built NuttX.
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2) Start the GDB server and wait until it is ready to accept GDB
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connections.
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3) Then run GDB like this:
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$ arm-none-eabi-gdb
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(gdb) target remote localhost:2331
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(gdb) mon reset
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(gdb) load nuttx
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(gdb) ... start debugging ...
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Loading code using J-Link Commander
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----------------------------------
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J-Link> r
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J-Link> loadbin <file> <address>
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J-Link> setpc <address of __start>
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J-Link> ... start debugging ...
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STATUS: As of this writing, I have no been successful writing to FLASH
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using the GDB server. I think that this is because of issues with GPNVM1
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settings and flash lock bits. In any event, the GDB server works great for
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debugging after writing the program to FLASH using SAM-BA.
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Writing to FLASH using SAM-BA
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Assumed starting configuration:
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1. You have installed the J-Link USB driver
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Using SAM-BA to write to FLASH:
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1. Start the SAM-BA application, selecting (1) the SAM-ICE/J-Link
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port, and (2) board = at91sam4e16-ek.
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2. The SAM-BA menu should appear.
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3. Select the FLASH tab and enable FLASH access
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4. "Send" the file to flash
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5. Enable "Boot from Flash (GPNVM1)
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6. Reset the board.
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STATUS: Works great!
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LEDs
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LEDs
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^^^^
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^^^^
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@ -270,17 +324,20 @@ Serial Console
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^^^^^^^^^^^^^^
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^^^^^^^^^^^^^^
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By default, all of these configurations use UART0 for the NuttX serial
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By default, all of these configurations use UART0 for the NuttX serial
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console. UART0 corresponds to the DB-9 connector labelled "UART". This
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console. UART0 corresponds to the DB-9 connector J17 labelled "DBGU".
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is a male connector and will require a female-to-female, NUL modem cable
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This is a male connector and will require a female-to-female, NUL modem
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to connect to a PC.
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cable to connect to a PC.
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An alternate is USART1 which connects to the other DB-9 connector labeled
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An alternate is USART1 which connects to the other DB-9 connector labelled
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"USART". USART1 is not enabled by default unless specifically noted
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"USART1". USART1 is not enabled by default unless specifically noted
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otherwise in the configuration description. A NUL modem cable must be
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otherwise in the configuration description. A NUL modem cable must be
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used with the port as well.
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used with the port as well.
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NOTE: One of the USART1 pins is shared with the audio CODEC. The audio
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NOTE: To avoid any electrical conflict, the RS232 and RS485 transceiver
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CODEC cannot be used of USART1 is enabled.
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are isolated from the receiving line PA21.
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- Chose RS485 channel: Close 1-2 pins on JP11 and set PA23 to high level
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- Chose RS232 channel: Close 2-3 pins on JP11 and set PA23 to low level
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By default serial console is configured for 115000, 8-bit, 1 stop bit, and
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By default serial console is configured for 115000, 8-bit, 1 stop bit, and
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no parity.
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no parity.
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@ -54,17 +54,17 @@
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************************************************************************************/
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************************************************************************************/
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/* Clocking *************************************************************************/
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/* Clocking *************************************************************************/
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/* After power-on reset, the SAM4E16 device is running on a 4MHz internal RC. These
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/* After power-on reset, the SAM4E16 device is running out of the Master Clock using
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* definitions will configure clocking
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* the Fast RC Oscillator running at 4 MHz.
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*
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*
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* MAINOSC: Frequency = 12MHz (crysta)
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* MAINOSC: Frequency = 12MHz (crystal)
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*
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*
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* CONFIG_SAM4EEK_120MHZ
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* CONFIG_SAM4EEK_120MHZ
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* PLLA: PLL Divider = 1, Multiplier = 20 to generate PLLACK = 240MHz
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* PLLA: PLL Divider = 1, Multiplier = 20 to generate PLLACK = 240MHz
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* Master Clock (MCK): Source = PLLACK, Prescalar = 1 to generate MCK = 120MHz
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* Master Clock (MCK): Source = PLLACK, Prescalar = 1 to generate MCK = 120MHz
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* CPU clock: 120MHz
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* CPU clock: 120MHz
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*
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*
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* CONFIG_SAM4EEK_196MHZ
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* CONFIG_SAM4EEK_96MHZ
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* PLLA: PLL Divider = 1, Multiplier = 16 to generate PLLACK = 192MHz
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* PLLA: PLL Divider = 1, Multiplier = 16 to generate PLLACK = 192MHz
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* Master Clock (MCK): Source = PLLACK, Prescalar = 1 to generate MCK = 96MHz
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* Master Clock (MCK): Source = PLLACK, Prescalar = 1 to generate MCK = 96MHz
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* CPU clock: 96MHz
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* CPU clock: 96MHz
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@ -85,9 +85,9 @@
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*/
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*/
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#ifdef CONFIG_SAM4EEK_120MHZ
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#ifdef CONFIG_SAM4EEK_120MHZ
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# define BOARD_CKGR_PLLAR_MUL (20 << PMC_CKGR_PLLAR_MUL_SHIFT)
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# define BOARD_CKGR_PLLAR_MUL (19 << PMC_CKGR_PLLAR_MUL_SHIFT)
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#else
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#else
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# define BOARD_CKGR_PLLAR_MUL (16 << PMC_CKGR_PLLAR_MUL_SHIFT)
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# define BOARD_CKGR_PLLAR_MUL (15 << PMC_CKGR_PLLAR_MUL_SHIFT)
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#endif
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#endif
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#define BOARD_CKGR_PLLAR_STMODE PMC_CKGR_PLLAR_STMODE_FAST
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#define BOARD_CKGR_PLLAR_STMODE PMC_CKGR_PLLAR_STMODE_FAST
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@ -116,7 +116,6 @@
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# define BOARD_MCK_FREQUENCY (120000000) /* MCK: PLLACK / 2 */
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# define BOARD_MCK_FREQUENCY (120000000) /* MCK: PLLACK / 2 */
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# define BOARD_CPU_FREQUENCY (120000000) /* CPU: MCK */
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# define BOARD_CPU_FREQUENCY (120000000) /* CPU: MCK */
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#else
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#else
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# define BOARD_MAINOSC_FREQUENCY (12000000) /* MAINOSC: 12MHz crystal on-board */
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# define BOARD_PLLA_FREQUENCY (192000000) /* PLLACK: 16 * 12Mhz / 1 */
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# define BOARD_PLLA_FREQUENCY (192000000) /* PLLACK: 16 * 12Mhz / 1 */
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# define BOARD_MCK_FREQUENCY (96000000) /* MCK: PLLACK / 2 */
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# define BOARD_MCK_FREQUENCY (96000000) /* MCK: PLLACK / 2 */
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# define BOARD_CPU_FREQUENCY (96000000) /* CPU: MCK */
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# define BOARD_CPU_FREQUENCY (96000000) /* CPU: MCK */
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@ -33,7 +33,7 @@
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*
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*
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****************************************************************************/
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****************************************************************************/
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/* The SAM4E16 has 1025KB of FLASH beginning at address 0x0008:0000,
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/* The SAM4E16 has 1024KB of FLASH beginning at address 0x0040:0000,
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* 128KB of SRAM beginning at address 0x2000:0000. When booting from FLASH,
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* 128KB of SRAM beginning at address 0x2000:0000. When booting from FLASH,
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* FLASH memory is aliased to address 0x0000:0000 where the code expects to
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* FLASH memory is aliased to address 0x0000:0000 where the code expects to
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* begin execution by jumping to the entry point in the 0x0800:0000 address
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* begin execution by jumping to the entry point in the 0x0800:0000 address
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@ -42,7 +42,7 @@
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MEMORY
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MEMORY
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{
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{
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flash (rx) : ORIGIN = 0x00080000, LENGTH = 1024K
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flash (rx) : ORIGIN = 0x00400000, LENGTH = 1024K
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sram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
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sram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
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}
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}
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@ -235,6 +235,18 @@
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#define IRQ_WAKU SAM_IRQ_PA19
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#define IRQ_WAKU SAM_IRQ_PA19
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#define IRQ_TAMP SAM_IRQ_PA20
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#define IRQ_TAMP SAM_IRQ_PA20
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/* USART1: To avoid any electrical conflict, the RS232 and RS485 transceiver
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* are isolated from the receiving line PA21.
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*
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* - Chose RS485 channel: Close 1-2 pins on JP11 and set PA23 to high level
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* - Chose RS232 channel: Close 2-3 pins on JP11 and set PA23 to low level
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*/
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#define GPIO_RS232_ENABLE (GPIO_OUTPUT | GPIO_CFG_DEFAULT | \
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GPIO_OUTPUT_CLEAR | GPIO_PORT_PIOA | GPIO_PIN21)
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#define GPIO_RS485_ENABLE (GPIO_OUTPUT | GPIO_CFG_DEFAULT | \
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GPIO_OUTPUT_SET | GPIO_PORT_PIOA | GPIO_PIN21)
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/* SD Card Detect */
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/* SD Card Detect */
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#define GPIO_MCI_CD (GPIO_INPUT | GPIO_CFG_PULLUP | GPIO_PORT_PIOA | GPIO_PIN25)
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#define GPIO_MCI_CD (GPIO_INPUT | GPIO_CFG_PULLUP | GPIO_PORT_PIOA | GPIO_PIN25)
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#include "sam4e-ek.h"
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#include "sam4e-ek.h"
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/************************************************************************************
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/************************************************************************************
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* Definitions
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* Pre-processor Definitions
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************************************************************************************/
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************************************************************************************/
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/************************************************************************************
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/************************************************************************************
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* Private Functions
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* Private Functions
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************************************************************************************/
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************************************************************************************/
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/************************************************************************************
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* Name: board_config_usart1
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*
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* Description:
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* USART1: To avoid any electrical conflict, the RS232 and RS485 transceiver are
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* isolated from the receiving line PA21.
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*
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* - Chose RS485 channel: Close 1-2 pins on JP11 and set PA23 to high level
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* - Chose RS232 channel: Close 2-3 pins on JP11 and set PA23 to low level
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*
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************************************************************************************/
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#ifdef CONFIG_SAM34_USART1
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static inline void board_config_usart1(void)
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{
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#if defined(CONFIG_USART1_ISUART)
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(void)sam_configgpio(GPIO_RS232_ENABLE);
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#else /* if defined(CONFIG_USART1_RS485) */
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(void)sam_configgpio(GPIO_RS485_ENABLE);
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#endif
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}
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#else
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# define board_config_usart1()
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#endif
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/************************************************************************************
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/************************************************************************************
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* Public Functions
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* Public Functions
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************************************************************************************/
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************************************************************************************/
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@ -70,6 +95,10 @@
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void sam_boardinitialize(void)
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void sam_boardinitialize(void)
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{
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{
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/* Configure USART1 for RS-232/RS-485 operation */
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board_config_usart1();
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/* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak function
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/* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak function
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* sam_spiinitialize() has been brought into the link.
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* sam_spiinitialize() has been brought into the link.
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*/
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*/
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