SAML21 USB: Add device side register defintiions
This commit is contained in:
Gregory Nutt
parent
b6629c0745
commit
d298b8048c
@ -57,30 +57,91 @@
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/* Common USB Device/Host Register Offsets */
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#define SAM_USB_CTRLA_OFFSET 0x0000 /* Control A Register */
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#define SAM_USB_SYNCBUSY_OFFSET 0x0002 /* Synchronization Busy Register */
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#define SAM_USB_QOSCTRL_OFFSET 0x0003 /* QOS Control Register */
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#define SAM_USB_FSMSTATUS_OFFSET 0x000d /* Finite State Machine Register */
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#define SAM_USB_DESCADD_OFFSET 0x0024 /* Descriptor Address Register */
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#define SAM_USB_PADCAL_OFFSET 0x0028 /* Pad Calibration Register */
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#define SAM_USB_CTRLA_OFFSET 0x0000 /* Control A Register */
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#define SAM_USB_SYNCBUSY_OFFSET 0x0002 /* Synchronization Busy Register */
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#define SAM_USB_QOSCTRL_OFFSET 0x0003 /* QOS Control Register */
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#define SAM_USB_FSMSTATUS_OFFSET 0x000d /* Finite State Machine Register */
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#define SAM_USB_DESCADD_OFFSET 0x0024 /* Descriptor Address Register */
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#define SAM_USB_PADCAL_OFFSET 0x0028 /* Pad Calibration Register */
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/* USB Device Register Offsets */
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#define SAM_USBDEV_CTRLB_OFFSET 0x0008 /* Control B Register */
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#define SAM_USBDEV_DADD_OFFSET 0x000a /* Device Address Register */
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#define SAM_USBDEV_STATUS_OFFSET 0x000c /* Status Register */
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#define SAM_USBDEV_FNUM_OFFSET 0x0010 /* Device Frame Number Register */
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#define SAM_USBDEV_INTENCLR_OFFSET 0x0014 /* Device Ineterrupt Enable Clear Register */
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#define SAM_USBDEV_INTENSET_OFFSET 0x0018 /* Device interrupt Enable Set Register */
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#define SAM_USBDEV_INTFLAG_OFFSET 0x001c /* Device Interrupt Flag Register */
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#define SAM_USBDEV_EPINTSMRY_OFFSET 0x0020 /* Endpoint Interrupt Summary Register */
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/* Endpoint Register n offset */
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#define SAM_USBDEV_EP_OFFSET(n) (0x0100 + ((n) << 4))
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/* The following are then relative to the endpoint register n offset */
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#define SAM_USBDEV_EPCFG_OFFSET 0x0000 /* Device Endpoint Configuration Register */
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#define SAM_USBDEV_EPSTATUSCLR_OFFSET 0x0004 /* Endpoint Status Clear Register */
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#define SAM_USBDEV_EPSTATUSSET_OFFSET 0x0005 /* Endpoint Status Set Register */
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#define SAM_USBDEV_EPSTATUS_OFFSET 0x0006 /* Endpoint Status Register */
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#define SAM_USBDEV_EPINTFLAG_OFFSET 0x0007 /* Device Endpoint Interrupt Flag Register */
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#define SAM_USBDEV_EPINTENCLR_OFFSET 0x0008 /* Device Endpoint Interrupt Enable Register */
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#define SAM_USBDEV_EPINTENSET_OFFSET 0x0009 /* Device Endpoint Interrupt Set Register */
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#define SAM_USBDEV_EPnCFG_OFFSET(n) (SAM_USBDEV_EP_OFFSET(n)+SAM_USBDEV_EPCFG_OFFSET)
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#define SAM_USBDEV_EPnSTATUSCLR_OFFSET(n) (SAM_USBDEV_EP_OFFSET(n)+SAM_USBDEV_EPSTATUSCLR_OFFSET)
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#define SAM_USBDEV_EPnSTATUSSET_OFFSET(n) (SAM_USBDEV_EP_OFFSET(n)+SAM_USBDEV_EPSTATUSSET_OFFSET)
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#define SAM_USBDEV_EPnSTATUS_OFFSET(n) (SAM_USBDEV_EP_OFFSET(n)+SAM_USBDEV_EPSTATUS_OFFSET)
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#define SAM_USBDEV_EPnINTFLAG_OFFSET(n) (SAM_USBDEV_EP_OFFSET(n)+SAM_USBDEV_EPINTFLAG_OFFSET)
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#define SAM_USBDEV_EPnINTENCLR_OFFSET(n) (SAM_USBDEV_EP_OFFSET(n)+SAM_USBDEV_EPINTENCLR_OFFSET)
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#define SAM_USBDEV_EPnINTENSET_OFFSET(n) (SAM_USBDEV_EP_OFFSET(n)+SAM_USBDEV_EPINTENSET_OFFSET)
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/* Device Endpoint Descriptor */
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#define SAM_USBDEV_ADDR_OFFSET 0x0000 /* Address of Data buffer (Both banks) */
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#define SAM_USBDEV_PKTSIZE_OFFSET 0x0004 /* Packet Size (Both banks) */
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#define SAM_USBDEV_EXTREG_OFFSET 0x0008 /* Extended Register (Bank 0 only) */
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#define SAM_USBDEV_STATUSBK_OFFSET 0x000a /* Device Status Bank (Both banks) */
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/* USB Host Register Offsets */
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/* USB register addresses ******************************************************************/
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/* Common USB Device/Host Register Addresses */
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#define SAM_USB_CTRLA (SAM_USB_BASE+SAM_USB_CTRLA_OFFSET)
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#define SAM_USB_SYNCBUSY (SAM_USB_BASE+SAM_USB_SYNCBUSY_OFFSET)
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#define SAM_USB_QOSCTRL (SAM_USB_BASE+SAM_USB_QOSCTRL_OFFSET)
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#define SAM_USB_FSMSTATUS (SAM_USB_BASE+SAM_USB_FSMSTATUS_OFFSET)
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#define SAM_USB_DESCADD (SAM_USB_BASE+SAM_USB_DESCADD_OFFSET)
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#define SAM_USB_PADCAL (SAM_USB_BASE+SAM_USB_PADCAL_OFFSET)
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#define SAM_USB_CTRLA (SAM_USB_BASE+SAM_USB_CTRLA_OFFSET)
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#define SAM_USB_SYNCBUSY (SAM_USB_BASE+SAM_USB_SYNCBUSY_OFFSET)
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#define SAM_USB_QOSCTRL (SAM_USB_BASE+SAM_USB_QOSCTRL_OFFSET)
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#define SAM_USB_FSMSTATUS (SAM_USB_BASE+SAM_USB_FSMSTATUS_OFFSET)
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#define SAM_USB_DESCADD (SAM_USB_BASE+SAM_USB_DESCADD_OFFSET)
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#define SAM_USB_PADCAL (SAM_USB_BASE+SAM_USB_PADCAL_OFFSET)
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/* USB Device Register Addresses */
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#define SAM_USBDEV_CTRLB (SAM_USB_BASE+SAM_USBDEV_CTRLB_OFFSET)
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#define SAM_USBDEV_DADD (SAM_USB_BASE+SAM_USBDEV_DADD_OFFSET)
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#define SAM_USBDEV_STATUS (SAM_USB_BASE+SAM_USBDEV_STATUS_OFFSET)
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#define SAM_USBDEV_FNUM (SAM_USB_BASE+SAM_USBDEV_FNUM_OFFSET)
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#define SAM_USBDEV_INTENCLR (SAM_USB_BASE+SAM_USBDEV_INTENCLR_OFFSET)
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#define SAM_USBDEV_INTENSET (SAM_USB_BASE+SAM_USBDEV_INTENSET_OFFSET)
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#define SAM_USBDEV_INTFLAG (SAM_USB_BASE+SAM_USBDEV_INTFLAG_OFFSET)
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#define SAM_USBDEV_EPINTSMRY (SAM_USB_BASE+SAM_USBDEV_EPINTSMRY_OFFSET)
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/* Endpoint Register n Base Address */
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#define SAM_USBDEV_EP_BASE(n) (SAM_USB_BASE+SAM_USBDEV_EP_OFFSET(n))
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/* The following are then relative to the endpoint register n offset */
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#define SAM_USBDEV_EPCFG(n) (SAM_USBDEV_EP_BASE(n)+SAM_USBDEV_EPCFG_OFFSET)
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#define SAM_USBDEV_EPSTATUSCLR(n) (SAM_USBDEV_EP_BASE(n)+SAM_USBDEV_EPSTATUSCLR_OFFSET)
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#define SAM_USBDEV_EPSTATUSSET(n) (SAM_USBDEV_EP_BASE(n)+SAM_USBDEV_EPSTATUSSET_OFFSET)
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#define SAM_USBDEV_EPSTATUS(n) (SAM_USBDEV_EP_BASE(n)+SAM_USBDEV_EPSTATUS_OFFSET)
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#define SAM_USBDEV_EPINTFLAG(n) (SAM_USBDEV_EP_BASE(n)+SAM_USBDEV_EPINTFLAG_OFFSET)
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#define SAM_USBDEV_EPINTENCLR(n) (SAM_USBDEV_EP_BASE(n)+SAM_USBDEV_EPINTENCLR_OFFSET)
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#define SAM_USBDEV_EPINTENSET(n) (SAM_USBDEV_EP_BASE(n)+SAM_USBDEV_EPINTENSET_OFFSET)
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/* USB Host Register Addresses */
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/* USB register bit definitions ************************************************************/
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@ -89,61 +150,214 @@
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/* Control A Register */
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#define USB_CTRLA_SWRST (1 << 0) /* Bit 0: Software reset */
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#define USB_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable */
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#define USB_CTRLA_RUNSTBY (1 << 2) /* Bit 2: Run in standby */
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#define USB_CTRLA_MODE (1 << 7) /* Bit 7: Operating mode */
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# define USB_CTRLA_MODE_DEVICE (0) /* 0 = USB device mode */
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# define USB_CTRLA_MODE (1 << 7) /* 1 = USB hose mode */
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#define USB_CTRLA_SWRST (1 << 0) /* Bit 0: Software reset */
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#define USB_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable */
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#define USB_CTRLA_RUNSTBY (1 << 2) /* Bit 2: Run in standby */
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#define USB_CTRLA_MODE (1 << 7) /* Bit 7: Operating mode */
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# define USB_CTRLA_MODE_DEVICE (0) /* 0 = USB device mode */
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# define USB_CTRLA_MODE (1 << 7) /* 1 = USB hose mode */
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/* Synchronization Busy Register */
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#define USB_SYNCBUSY_SWRST (1 << 0) /* Bit 0: Software reset status */
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#define USB_SYNCBUSY_ENABLE (1 << 1) /* Bit 1: Enable status */
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#define USB_SYNCBUSY_SWRST (1 << 0) /* Bit 0: Software reset status */
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#define USB_SYNCBUSY_ENABLE (1 << 1) /* Bit 1: Enable status */
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/* QOS Control Register */
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#define USB_QOSCTRL_CQOS_SHIFT (0) /* Bit 0-1: Data quality of service */
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#define USB_QOSCTRL_CQOS_MASK (3 << USB_QOSCTRL_CQOS_SHIFT)
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# define USB_QOSCTRL_CQOS(n) ((uint8_t)(n) << USB_QOSCTRL_CQOS_SHIFT)
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#define USB_QOSCTRL_DQOS_SHIFT (2) /* Bit 2-3: Configuration qualilty of service */
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#define USB_QOSCTRL_DQOS_MASK (3 << USB_QOSCTRL_DQOS_SHIFT)
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# define USB_QOSCTRL_DQOS(n) ((uint8_t)(n) << USB_QOSCTRL_DQOS_SHIFT)
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#define USB_QOSCTRL_CQOS_SHIFT (0) /* Bit 0-1: Data quality of service */
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#define USB_QOSCTRL_CQOS_MASK (3 << USB_QOSCTRL_CQOS_SHIFT)
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# define USB_QOSCTRL_CQOS(n) ((uint8_t)(n) << USB_QOSCTRL_CQOS_SHIFT)
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#define USB_QOSCTRL_DQOS_SHIFT (2) /* Bit 2-3: Configuration qualilty of service */
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#define USB_QOSCTRL_DQOS_MASK (3 << USB_QOSCTRL_DQOS_SHIFT)
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# define USB_QOSCTRL_DQOS(n) ((uint8_t)(n) << USB_QOSCTRL_DQOS_SHIFT)
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/* Finite State Machine Register */
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#define USB_FSMSTATUS_SHIFT (0) /* Bits 0-6: Finite state machine status */
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#define USB_FSMSTATUS_MASK (0x7f << USB_FSMSTATUS_SHIFT)
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# define USB_FSMSTATUS_OFF (0x01 << USB_FSMSTATUS_SHIFT) /* Powered-off, disconnect, disabled state */
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# define USB_FSMSTATUS_ON (0x02 << USB_FSMSTATUS_SHIFT) /* Idle and Active states */
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# define USB_FSMSTATUS_SUSPEND (0x04 << USB_FSMSTATUS_SHIFT)
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# define USB_FSMSTATUS_SLEEP (0x08 << USB_FSMSTATUS_SHIFT)
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# define USB_FSMSTATUS_DNRESUME (0x10 << USB_FSMSTATUS_SHIFT) /* Down stream resume */
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# define USB_FSMSTATUS_UPRESUME (0x20 << USB_FSMSTATUS_SHIFT) /* Up stream resume */
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# define USB_FSMSTATUS_RESET (0x40 << USB_FSMSTATUS_SHIFT) /* USB lines reset */
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#define USB_FSMSTATUS_SHIFT (0) /* Bits 0-6: Finite state machine status */
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#define USB_FSMSTATUS_MASK (0x7f << USB_FSMSTATUS_SHIFT)
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# define USB_FSMSTATUS_OFF (0x01 << USB_FSMSTATUS_SHIFT) /* Powered-off, disconnect, disabled state */
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# define USB_FSMSTATUS_ON (0x02 << USB_FSMSTATUS_SHIFT) /* Idle and Active states */
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# define USB_FSMSTATUS_SUSPEND (0x04 << USB_FSMSTATUS_SHIFT)
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# define USB_FSMSTATUS_SLEEP (0x08 << USB_FSMSTATUS_SHIFT)
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# define USB_FSMSTATUS_DNRESUME (0x10 << USB_FSMSTATUS_SHIFT) /* Down stream resume */
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# define USB_FSMSTATUS_UPRESUME (0x20 << USB_FSMSTATUS_SHIFT) /* Up stream resume */
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# define USB_FSMSTATUS_RESET (0x40 << USB_FSMSTATUS_SHIFT) /* USB lines reset */
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/* Descriptor Address Register (32-bit address) */
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/* Pad Calibration Register */
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#define USB_PADCAL_TRANSP_SHIFT (0) /* Bit 0-4: Trimmable output driver impedance P */
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#define USB_PADCAL_TRANSP_MASK (31 << USB_PADCAL_TRANSP_SHIFT)
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# define USB_PADCAL_TRANSP(n) ((uint16_t)(n) << USB_PADCAL_TRANSP_SHIFT)
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#define USB_PADCAL_TRANSN_SHIFT (6) /* Bit 7-9: Trimmable output driver impedance N */
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#define USB_PADCAL_TRANSN_MASK (31 << USB_PADCAL_TRANSN_SHIFT)
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# define USB_PADCAL_TRANSN(n) ((uint16_t)(n) << USB_PADCAL_TRANSN_SHIFT)
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#define USB_PADCAL_TRIM_SHIFT (12) /* Bit 12-14: Trim bits for DP/DM */
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#define USB_PADCAL_TRIM_MASK (7 << USB_PADCAL_TRIM_SHIFT)
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# define USB_PADCAL_TRIM(n) ((uint16_t)(n) << USB_PADCAL_TRIM_SHIFT)
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#define USB_PADCAL_TRANSP_SHIFT (0) /* Bit 0-4: Trimmable output driver impedance P */
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#define USB_PADCAL_TRANSP_MASK (31 << USB_PADCAL_TRANSP_SHIFT)
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# define USB_PADCAL_TRANSP(n) ((uint16_t)(n) << USB_PADCAL_TRANSP_SHIFT)
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#define USB_PADCAL_TRANSN_SHIFT (6) /* Bit 7-9: Trimmable output driver impedance N */
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#define USB_PADCAL_TRANSN_MASK (31 << USB_PADCAL_TRANSN_SHIFT)
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# define USB_PADCAL_TRANSN(n) ((uint16_t)(n) << USB_PADCAL_TRANSN_SHIFT)
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#define USB_PADCAL_TRIM_SHIFT (12) /* Bit 12-14: Trim bits for DP/DM */
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#define USB_PADCAL_TRIM_MASK (7 << USB_PADCAL_TRIM_SHIFT)
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# define USB_PADCAL_TRIM(n) ((uint16_t)(n) << USB_PADCAL_TRIM_SHIFT)
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/* USB Device Register Offsets */
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/* Control B Register */
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#define USBDEV_CTRLB_DETACH (1 << 0) /* Bit 0: Detach */
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#define USBDEV_CTRLB_UPRSM (1 << 1) /* Bit 1: Upstresm resume */
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#define USBDEV_CTRLB_SPDCONF_SHIFT (2) /* Bits 2-3: Speed configuration */
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#define USBDEV_CTRLB_SPDCONF_MASK (3 << USBDEV_CTRLB_SPDCONF_SHIFT)
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# define USBDEV_CTRLB_SPDCONF_LOW (0 << USBDEV_CTRLB_SPDCONF_SHIFT) /* Low speed */
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# define USBDEV_CTRLB_SPDCONF_FULL (1 << USBDEV_CTRLB_SPDCONF_SHIFT) /* Full speed */
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#define USBDEV_CTRLB_NREPLY (1 << 4) /* Bit 4: No reply except SETUP token */
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#define USBDEV_CTRLB_GNAK (1 << 9) /* Bit 9: Global NAK */
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#define USBDEV_CTRLB_LPMHDSK_SHIFT (10) /* Bits 10-11: Link power management handshake */
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#define USBDEV_CTRLB_LPMHDSK_MASK (3 << USBDEV_CTRLB_LPMHDSK_SHIFT)
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# define USBDEV_CTRLB_LPMHDSK_NONE (0 << USBDEV_CTRLB_LPMHDSK_SHIFT) /* No handshake, LPM not supported */
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# define USBDEV_CTRLB_LPMHDSK_ACK (1 << USBDEV_CTRLB_LPMHDSK_SHIFT)
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# define USBDEV_CTRLB_LPMHDSK_NYET (2 << USBDEV_CTRLB_LPMHDSK_SHIFT)
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/* Device Address Register */
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#define USBDEV_DADD_SHIFT (0) /* Bits 0-6: Device address */
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#define USBDEV_DADD_MASK (0x7f << USBDEV_DADD_SHIFT)
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# define USBDEV_DADD(n) ((uint8_t)(n) << USBDEV_DADD_SHIFT)
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#define USBDEV_DADD_ADDEN (1 << 7) /* Bit 7: Device address enable */
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/* Status Register */
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#define USBDEV_STATUS_SPEED_SHIFT (0) /* Bits 0-1: Speed status */
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#define USBDEV_STATUS_SPEED_MASK (3 << USBDEV_STATUS_SPEED_SHIFT)
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# define USBDEV_STATUS_SPEED_LOW (0 << USBDEV_STATUS_SPEED_SHIFT) /* Low speed */
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# define USBDEV_STATUS_SPEED_FULL (1 << USBDEV_STATUS_SPEED_SHIFT) /* Full speed */
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#define USBDEV_STATUS_LNSTATE_SHIFT (6) /* Bits 6-7: USB line status */
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#define USBDEV_STATUS_LNSTATE_MASK (3 << USBDEV_STATUS_LNSTATE_SHIFT)
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# define USBDEV_STATUS_LNSTATE_SE0 (0 << USBDEV_STATUS_LNSTATE_SHIFT) /* SE0/RESET */
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# define USBDEV_STATUS_LNSTATE_LJFK (1 << USBDEV_STATUS_LNSTATE_SHIFT) /* LS-J or FS-K */
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# define USBDEV_STATUS_LNSTATE_LKFJ (2 << USBDEV_STATUS_LNSTATE_SHIFT) /* LS-K or FS-L */
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/* Device Frame Number Register */
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#define USBDEV_MFNUM_SHIFT (0) /* Bits 0-2: Micro-frame number */
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#define USBDEV_MFNUM_MASK (7 << USBDEV_MFNUM_SHIFT)
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#define USBDEV_FNUM_SHIFT (3) /* Bits 3-13: Frame number */
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#define USBDEV_FNUM_MASK (0x7ff << USBDEV_FNUM_SHIFT)
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#define USBDEV_FNUM_FNCERR (1 << 15) /* Bit 15: Frame number CRC error */
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/* Common definitions for Device Ineterrupt Enable Clear Register, Device interrupt
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* Enable Set Register, and SAM_USBDEV_INTFLAG_OFFSET
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*/
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#define USBDEV_INT_SUSPEND (1 << 0) /* Bit 0: Suspend interrupt */
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#define USBDEV_INT_SOF (1 << 2) /* Bit 2: Start of frame interrupt */
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#define USBDEV_INT_EORST (1 << 3) /* Bit 3: End of reset interrupt */
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#define USBDEV_INT_WAKEUP (1 << 4) /* Bit 4: Wake-up interrupt */
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#define USBDEV_INT_EORSM (1 << 5) /* Bit 5: End of resume interrupt */
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#define USBDEV_INT_UPRSM (1 << 6) /* Bit 6: Upstream resume interrupt */
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#define USBDEV_INT_RAMACER (1 << 7) /* Bit 7: RAM access interrupt */
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#define USBDEV_INT_LPMNYET (1 << 8) /* Bit 8: Link power NotYet interrupt */
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#define USBDEV_INT_LPMSUSP (1 << 9) /* Bit 9: Link power suspend interrupt */
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/* Endpoint Interrupt Summary Register */
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#define USBDEV_EPINTSMRY_EPINT(n) (1 << (n))
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/* Device Endpoint Configuration Register */
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#define USBDEV_EPCFG_EPTYPE0_SHIFT (0) /* Bits 0-2: Endpoint type for OUT direction */
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#define USBDEV_EPCFG_EPTYPE0_MASK (7 << USBDEV_EPCFG_EPTYPE0_SHIFT)
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# define USBDEV_EPCCFG_EPTYPE0_DISABLED (0 << USBDEV_EPCFG_EPTYPE0_SHIFT) /* Bank 0 disabled */
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# define USBDEV_EPCCFG_EPTYPE0_CTRLOUT (1 << USBDEV_EPCFG_EPTYPE0_SHIFT) /* Bank 0 control SETUP/OUT */
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# define USBDEV_EPCCFG_EPTYPE0_ISOCOUT (2 << USBDEV_EPCFG_EPTYPE0_SHIFT) /* Bank 0 isochronous OUT */
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# define USBDEV_EPCCFG_EPTYPE0_BULKOUT (3 << USBDEV_EPCFG_EPTYPE0_SHIFT) /* Bank 0 bulk OUT */
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# define USBDEV_EPCCFG_EPTYPE0_INTOUT (4 << USBDEV_EPCFG_EPTYPE0_SHIFT) /* Bank 0 interrupt OUT */
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# define USBDEV_EPCCFG_EPTYPE0_DBIN (5 << USBDEV_EPCFG_EPTYPE0_SHIFT) /* Bank 0 dual bank IN */
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#define USBDEV_EPCFG_EPTYPE1_SHIFT (4) /* Bits 4-6: Endpoint type for IN direction */
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#define USBDEV_EPCFG_EPTYPE1_MASK (7 << USBDEV_EPCFG_EPTYPE1_SHIFT)
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# define USBDEV_EPCCFG_EPTYPE1_DISABLED (0 << USBDEV_EPCFG_EPTYPE1_SHIFT) /* Bank 1 disabled */
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# define USBDEV_EPCCFG_EPTYPE1_CTRLIN (1 << USBDEV_EPCFG_EPTYPE1_SHIFT) /* Bank 1 control IN */
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# define USBDEV_EPCCFG_EPTYPE1_ISOCIN (2 << USBDEV_EPCFG_EPTYPE1_SHIFT) /* Bank 1 isochronous IN */
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# define USBDEV_EPCCFG_EPTYPE1_BULKIN (3 << USBDEV_EPCFG_EPTYPE1_SHIFT) /* Bank 1 bulk IN */
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# define USBDEV_EPCCFG_EPTYPE1_INTIN (4 << USBDEV_EPCFG_EPTYPE1_SHIFT) /* Bank 1 interrupt IN */
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# define USBDEV_EPCCFG_EPTYPE1_DBOUT (5 << USBDEV_EPCFG_EPTYPE1_SHIFT) /* Bank 1 dual bank OUT */
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/* Common definitions for Endpoint Status Clear Register, Endpoint Status Set
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* Register, and Endpoint Status Set Register
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*/
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#define USBDEV_EPSTATUS_DTGLOUT (1 << 0) /* Bit 0: Data toggle OUT */
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#define USBDEV_EPSTATUS_DTGLIN (1 << 1) /* Bit 1: Data toggle IN */
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#define USBDEV_EPSTATUS_CURBK (1 << 2) /* Bit 2: Current bank */
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#define USBDEV_EPSTATUS_STALLRQ0 (1 << 4) /* Bit 4: Stall bank 0 request */
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#define USBDEV_EPSTATUS_STALLRQ1 (1 << 5) /* Bit 5: Stall bank 1 request */
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#define USBDEV_EPSTATUS_BK0RDY (1 << 6) /* Bit 6: Bank 0 ready */
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#define USBDEV_EPSTATUS_BK1RDY (1 << 7) /* Bit 7: Bank 1 ready */
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/* Common definitions for Device Endpoint Interrupt Flag Register, Device Endpoint
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* Interrupt Enable Register, and Device Endpoint Interrupt Set Register
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*/
|
||||
|
||||
#define USBDEV_EPINT_TRCPT0 (1 << 0) /* Bit 0: Transmit complete 0 interrupt */
|
||||
#define USBDEV_EPINT_TRCPT1 (1 << 1) /* Bit 1: Transmit complete 1 interrupt */
|
||||
#define USBDEV_EPINT_TRFAIL0 (1 << 2) /* Bit 2: Transmit fail 0 interrupt */
|
||||
#define USBDEV_EPINT_TRFAIL1 (1 << 3) /* Bit 3: Transmit fail 1 interrupt */
|
||||
#define USBDEV_EPINT_RXSTP (1 << 4) /* Bit 4: Received SETUP interrupt */
|
||||
#define USBDEV_EPINT_STALL0 (1 << 5) /* Bit 5: Transmit stall 0 interrupt */
|
||||
#define USBDEV_EPINT_STALL1 (1 << 6) /* Bit 5: Transmit stall 1 interrupt */
|
||||
|
||||
/* Device Endpoint Descriptor */
|
||||
|
||||
/* Address of Data buffer (Both banks, 32-bit address) */
|
||||
|
||||
/* Packet Size (Both banks) */
|
||||
|
||||
#define USBDEV_PKTSIZE_BYTECOUNT_SHIFT (0) /* Bits 0-5: */
|
||||
#define USBDEV_PKTSIZE_BYTECOUNT_MASK (0x3f << USBDEV_PKTSIZE_BYTECOUNT_SHIFT)
|
||||
# define USBDEV_PKTSIZE_BYTECOUNT(n) ((uint32_t)(n) << USBDEV_PKTSIZE_BYTECOUNT_SHIFT)
|
||||
#define USBDEV_PKTSIZE_MPKTSIZE_SHIFT (14) /* Bits 14-27: Multi-packet size */
|
||||
#define USBDEV_PKTSIZE_MPKTSIZE_MASK (0x3fff << USBDEV_PKTSIZE_MPKTSIZE_SHIFT)
|
||||
# define USBDEV_PKTSIZE_MPKTSIZE(n) ((uint32_t)(n) << USBDEV_PKTSIZE_MPKTSIZE_SHIFT)
|
||||
#define USBDEV_PKTSIZE_SIZE_SHIFT (28) /* Bits 28-30: Endpoint size */
|
||||
#define USBDEV_PKTSIZE_SIZE_MASK (7 << USBDEV_PKTSIZE_SIZE_SHIFT)
|
||||
# define USBDEV_PKTSIZE_SIZE_8B (0 << USBDEV_PKTSIZE_SIZE_SHIFT) /* 8 bytes */
|
||||
# define USBDEV_PKTSIZE_SIZE_16B (1 << USBDEV_PKTSIZE_SIZE_SHIFT) /* 16 bytes */
|
||||
# define USBDEV_PKTSIZE_SIZE_32B (2 << USBDEV_PKTSIZE_SIZE_SHIFT) /* 32 bytes */
|
||||
# define USBDEV_PKTSIZE_SIZE_64B (3 << USBDEV_PKTSIZE_SIZE_SHIFT) /* 64 bytes */
|
||||
# define USBDEV_PKTSIZE_SIZE_128B (4 << USBDEV_PKTSIZE_SIZE_SHIFT) /* 128 bytes (isoc only) */
|
||||
# define USBDEV_PKTSIZE_SIZE_256B (5 << USBDEV_PKTSIZE_SIZE_SHIFT) /* 256 bytes (isoc only) */
|
||||
# define USBDEV_PKTSIZE_SIZE_512B (6 << USBDEV_PKTSIZE_SIZE_SHIFT) /* 512 bytes (isoc only) */
|
||||
# define USBDEV_PKTSIZE_SIZE_1023B (7 << USBDEV_PKTSIZE_SIZE_SHIFT) /* 1023 bytes (isoc only) */
|
||||
#define USBDEV_PKTSIZE_AUTOZLP (1 << 31) /* Bit 31: Automatic zero length packet */
|
||||
|
||||
/* Extended Register (Bank 0 only) */
|
||||
|
||||
#define USBDEV_EXTREG_SUBPID_SHIFT (0) /* Bits 0-3: Sub PID */
|
||||
#define USBDEV_EXTREG_SUBPID_MASK (15 << USBDEV_EXTREG_SUBPID_SHIFT)
|
||||
# define USBDEV_EXTREG_SUBPID(n) ((uint16_t)(n) << USBDEV_EXTREG_SUBPID_SHIFT)
|
||||
#define USBDEV_EXTREG_VARIABLE_SHIFT (4) /* Bits 4-14: Variable */
|
||||
#define USBDEV_EXTREG_VARIABLE_MASK (0x7ff << USBDEV_EXTREG_VARIABLE_SHIFT)
|
||||
# define USBDEV_EXTREG_VARIABLE(n) ((uint16_t)(n) << USBDEV_EXTREG_VARIABLE_SHIFT)
|
||||
|
||||
/* Device Status Bank (Both banks) */
|
||||
|
||||
#define USBDEV_STATUSBK_CRCERR (1 << 0) /* Bit 0: CRC error */
|
||||
#define USBDEV_STATUSBK_ERRORFLOW (1 << 1) /* Bit 1: Error flow status */
|
||||
|
||||
/* USB Host Register Offsets */
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Types
|
||||
********************************************************************************************/
|
||||
|
||||
/* Device Endpoint Descriptor */
|
||||
|
||||
struct usbdev_epdesc_s
|
||||
{
|
||||
uint32_t addr; /* 0x0000-0x0003: Address of Data buffer (Both banks) */
|
||||
uint32_t pktsize; /* 0x0004-0x0007: Packet Size (Both banks) */
|
||||
uint16_t extreg; /* 0x0008-0x0009: Extended Register (Bank 0 only) */
|
||||
uint8_t stausbk; /* 0x000a-0x000a: Device Status Bank (Both banks) */
|
||||
uint8_t reserved[5]; /* 0x000b-0x000f: Both banks */
|
||||
};
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Data
|
||||
********************************************************************************************/
|
||||
|
||||
Loading…
Reference in New Issue
Block a user