arch/arm/src/lpc54xx: Bring in NXP support for external SDRAM.
This commit is contained in:
Gregory Nutt
parent
77728f49f1
commit
dab97de4ea
@ -253,6 +253,6 @@ config LPC54_EMC_STATIC
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config LPC54_EMC_DYNAMIC
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bool "EMC dynamic memory support"
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default n
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default y
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endmenu # LPC54xx Peripheral Selection
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@ -98,11 +98,11 @@ ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
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CHIP_CSRCS += lpc54_idle.c
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endif
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ifneq ($(CONFIG_LPC54_GPIOIRQ),y)
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ifeq ($(CONFIG_LPC54_GPIOIRQ),y)
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CHIP_CSRCS += lpc54_gpioirq.c
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endif
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ifneq ($(CONFIG_LPC54_EMC),y)
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ifeq ($(CONFIG_LPC54_EMC),y)
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CHIP_CSRCS += lpc54_emc.c
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endif
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@ -51,6 +51,7 @@
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#define LPC54_EMC_CS1 1
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#define LPC54_EMC_CS2 2
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#define LPC54_EMC_CS3 3
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#define LPC54_EMC_NCS 4
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/* Register offsets *********************************************************************************/
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@ -75,16 +76,16 @@
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/* Per-chip select dynamic memory registers */
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#define LPC54_EMC_DYNCS_OFFSET(n) (0x0100 + (n) << 5)
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#define LPC54_EMC_DYNCS_OFFSET(n) (0x0100 + ((uintptr_t)(n) << 5))
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#define LPC54_EMC_DYNCONFIG_OFFSET 0x0000 /* Configuration information for CSn */
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#define LPC54_EMC_DYNRASCAS_OFFSET 0x0004 /* RAS and CAS latencies for CSn */
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#define LPC54_EMC_DYNCONFIGn_OFFSET(n) (0x0100 + (n) << 5)
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#define LPC54_EMC_DYNRASCASn_OFFSET(n) (0x0104 + (n) << 5)
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#define LPC54_EMC_DYNCONFIGn_OFFSET(n) (0x0100 + ((uintptr_t)(n) << 5))
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#define LPC54_EMC_DYNRASCASn_OFFSET(n) (0x0104 + ((uintptr_t)(n) << 5))
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/* Per-chip select static memory registers */
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#define LPC54_EMC_STATCS_OFFSET(n) (0x0200 + (n) << 5)
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#define LPC54_EMC_STATCS_OFFSET(n) (0x0200 + ((uintptr_t)(n) << 5))
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#define LPC54_EMC_STATCONFIG_OFFSET 0x0000 /* Configuration for CSn */
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#define LPC54_EMC_STATWAITWEN_OFFSET 0x0004 /* Delay to write enable */
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#define LPC54_EMC_STATWAITOEN_OFFSET 0x0008 /* Delay to output enable */
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@ -93,13 +94,13 @@
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#define LPC54_EMC_STATWAITWR_OFFSET 0x0014 /* Delay from EMC_CS0 to a write access */
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#define LPC54_EMC_STATWAITTURN_OFFSET 0x0018 /* Number of bus turnaround cycles */
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#define LPC54_EMC_STATCONFIGn_OFFSET(n) (0x0200 + (n) << 5)
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#define LPC54_EMC_STATWAITWENn_OFFSET(n) (0x0204 + (n) << 5)
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#define LPC54_EMC_STATWAITOENn_OFFSET(n) (0x0208 + (n) << 5)
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#define LPC54_EMC_STATWAITRDn_OFFSET(n) (0x020c + (n) << 5)
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#define LPC54_EMC_STATWAITPAGEn_OFFSET(n) (0x0210 + (n) << 5)
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#define LPC54_EMC_STATWAITWRn_OFFSET(n) (0x0214 + (n) << 5)
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#define LPC54_EMC_STATWAITTURNn_OFFSET(n) (0x0218 + (n) << 5)
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#define LPC54_EMC_STATCONFIGn_OFFSET(n) (0x0200 + ((uintptr_t)(n) << 5))
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#define LPC54_EMC_STATWAITWENn_OFFSET(n) (0x0204 + ((uintptr_t)(n) << 5))
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#define LPC54_EMC_STATWAITOENn_OFFSET(n) (0x0208 + ((uintptr_t)(n) << 5))
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#define LPC54_EMC_STATWAITRDn_OFFSET(n) (0x020c + ((uintptr_t)(n) << 5))
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#define LPC54_EMC_STATWAITPAGEn_OFFSET(n) (0x0210 + ((uintptr_t)(n) << 5))
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#define LPC54_EMC_STATWAITWRn_OFFSET(n) (0x0214 + ((uintptr_t)(n) << 5))
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#define LPC54_EMC_STATWAITTURNn_OFFSET(n) (0x0218 + ((uintptr_t)(n) << 5))
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/* Register addresses *******************************************************************************/
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@ -163,8 +164,8 @@
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#define EMC_DYNCONTROL_CE (1 << 0) /* Bit 0: Dynamic memory clock enable */
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#define EMC_DYNCONTROL_CS (1 << 1) /* Bit 1: Dynamic memory clock control */
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#define EMC_DYNCONTROL_SR (1 << 2) /* Bit 2: Self-refresh request, EMCSREFREQ */
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#define EMC_DYNCONTROL_MMC (1 << 5) /* Bit 5 Memory clock control */
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#define EMC_DYNCONTROL_I_SHIFT (7) /* Bit 7-8: SDRAM initialization */ */
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#define EMC_DYNCONTROL_MMC (1 << 5) /* Bit 5: Memory clock control */
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#define EMC_DYNCONTROL_I_SHIFT (7) /* Bit 7-8: SDRAM initialization */
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#define EMC_DYNCONTROL_I_MASK (3 << EMC_DYNCONTROL_I_SHIFT)
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# define EMC_DYNCONTROL_I_NORMAL (0 << EMC_DYNCONTROL_I_SHIFT) /* Issue SDRAM NORMAL operation command */
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# define EMC_DYNCONTROL_I_MODE (1 << EMC_DYNCONTROL_I_SHIFT) /* Issue SDRAM MODE command */
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@ -182,6 +183,7 @@
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#define EMC_DYNREADCONFIG_SHIFT (0) /* Bits 0-1: Read data strategy */
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#define EMC_DYNREADCONFIG_MASK (3 << EMC_DYNREADCONFIG_SHIFT)
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# define EMC_DYNREADCONFIG(n) ((uint32_t)(n) << EMC_DYNREADCONFIG_SHIFT)
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# define EMC_DYNREADCONFIG_PLUS0 (1 << EMC_DYNREADCONFIG_SHIFT) /* Using EMCCLKDELAY */
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# define EMC_DYNREADCONFIG_PLUS1 (2 << EMC_DYNREADCONFIG_SHIFT) /* Plus one clock cycle using EMCCLKDELAY */
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# define EMC_DYNREADCONFIG_PLUS2 (3 << EMC_DYNREADCONFIG_SHIFT) /* Plus two clock cycles using EMCCLKDELAY */
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@ -214,7 +216,7 @@
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#define EMC_DYNDAL_SHIFT (0) /* Bits 0-3: Data-in to active command */
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#define EMC_DYNDAL_MASK (15 << EMC_DYNDAL_SHIFT)
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# define EMC_DYNDAL(n) ((uint32_t)((n)-1) << EMC_DYNDAL_SHIFT)
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# define EMC_DYNDAL(n) ((uint32_t)(n) << EMC_DYNDAL_SHIFT)
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/* Write recovery time */
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@ -263,6 +265,7 @@
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#define EMC_DYNCONFIG_
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#define EMC_DYNCONFIG_MD_SHIFT (3) /* Bits 3-4: Memory device */
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#define EMC_DYNCONFIG_MD_MASK (3 << EMC_DYNCONFIG_MD_SHIFT)
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# define EMC_DYNCONFIG_MD(n) ((uint32_t)(n) << EMC_DYNCONFIG_MD_SHIFT)
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# define EMC_DYNCONFIG_MD_SDRAM (0 << EMC_DYNCONFIG_MD_SHIFT) /* SDRAM */
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# define EMC_DYNCONFIG_MD_LPDRAM (1 << EMC_DYNCONFIG_MD_SHIFT) /* Low-power SDRAM */
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#define EMC_DYNCONFIG_AM0_SHIFT (7) /* Bits 7-12: See Table 656 in User Manual */
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@ -272,12 +275,16 @@
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#define EMC_DYNCONFIG_B (1 << 19) /* Bit 19: Buffer enable */
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#define EMC_DYNCONFIG_P (1 << 20) /* Bit 20: Write protect */
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#define EMC_DYNCONFIG_ADDRMAP_SHIFT EMC_DYNCONFIG_AM0_SHIFT
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#define EMC_DYNCONFIG_ADDRMAP_MASK (EMC_DYNCONFIG_AM0_MASK | EMC_DYNCONFIG_AM1)
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# define EMC_DYNCONFIG_ADDRMAP(n) ((uint32_t)(n) << EMC_DYNCONFIG_ADDRMAP_SHIFT)
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/* Dynamic Memory RAS and CAS Delay registers */
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#define EMC_DYNRASCAS_RAS_SHIFT (0) /* Bits 0-1: RAS latency */
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#define EMC_DYNRASCAS_RAS_MASK (3 << EMC_DYNRASCAS_RAS_SHIFT)
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# define EMC_DYNRASCAS_RAS(n) ((uint32_t)(n) << EMC_DYNRASCAS_RAS_SHIFT)
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#define EMC_DYNRASCAS_CAS_SHIFT (8) /* Bits 9-9: CAS latency */
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#define EMC_DYNRASCAS_CAS_SHIFT (8) /* Bits 8-9: CAS latency */
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#define EMC_DYNRASCAS_CAS_MASK (3 << EMC_DYNRASCAS_CAS_SHIFT)
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# define EMC_DYNRASCAS_CAS(n) ((uint32_t)(n) << EMC_DYNRASCAS_CAS_SHIFT)
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@ -619,7 +619,7 @@
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#define SYSCON_EMCCLKDIV_DIV_SHIFT (9) /* Bits 0-7: Clock divider value */
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#define SYSCON_EMCCLKDIV_DIV_MASK (0xff <<SYSCON_EMCCLKDIV_DIV_SHIFT)
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# define SYSCON_EMCCLKDIV_DIV(n) ((uint32)((n)-1) <<SYSCON_EMCCLKDIV_DIV_SHIFT)
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# define SYSCON_EMCCLKDIV_DIV(n) ((uint32_t)((n)-1) <<SYSCON_EMCCLKDIV_DIV_SHIFT)
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#define SYSCON_EMCCLKDIV_RESET (1 << 29) /* Bit 29: Resets the divider counter */
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#define SYSCON_EMCCLKDIV_ HALT (1 << 30) /* Bit 30: Halts the divider counter */
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#define SYSCON_EMCCLKDIV_REQFLAG (1 << 31) /* Bit 31: Divider status flag */
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@ -45,13 +45,174 @@
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <nuttx/clock.h>
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#include "up_arch.h"
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#include "chip/lpc54_syscon.h"
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#include "chip/lpc54_emc.h"
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#include "lpc54_emc.h"
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#ifdef CONFIG_LPC54_EMC
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define EMC_SDRAM_MODE_CL_SHIFT (4)
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#define EMC_SDRAM_MODE_CL_MASK (7 << EMC_SDRAM_MODE_CL_SHIFT)
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#define EMC_DYNCTL_COLUMNBASE_SHIFT (0)
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#define EMC_DYNCTL_COLUMNBASE_MASK (3 << EMC_DYNCTL_COLUMNBASE_SHIFT)
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#define EMC_DYNCTL_COLUMNPLUS_SHIFT (3)
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#define EMC_DYNCTL_COLUMNPLUS_MASK (3 << EMC_DYNCTL_COLUMNPLUS_SHIFT)
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#define EMC_DYNCTL_BUSWIDTH_MASK (0x80)
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#define EMC_DYNCTL_BUSADDRMAP_MASK (0x20)
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#define EMC_DYNCTL_DEVBANKS_BITS_MASK (0x1c)
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#define EMC_SDRAM_BANKCS_BA0_MASK (uint32_t)(0x2000)
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#define EMC_SDRAM_BANKCS_BA1_MASK (uint32_t)(0x4000)
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#define EMC_SDRAM_BANKCS_BA_MASK (EMC_SDRAM_BANKCS_BA0_MASK | EMC_SDRAM_BANKCS_BA1_MASK)
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#define EMC_REFRESH_CLOCK_SCALE 16
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#define EMC_SDRAM_WAIT_CYCLES 2000
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#define MHZ_PER_HZ 1000000
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/****************************************************************************
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* Private Data
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****************************************************************************/
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static const uintptr_t g_dram_csbase[LPC54_EMC_NCS] =
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{
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LPC54_DRAMCS0_BASE, LPC54_DRAMCS1_BASE, LPC54_DRAMCS2_BASE,
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LPC54_DRAMCS3_BASE
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};
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: lpc54_emc_timercycles
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*
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* Description:
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* Convert nanoseconds to EMC clock cycles and clip to the provided range.
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*
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* Input Parameters:
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* nsec - Nanoseconds to be converted.
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* lower - Lower valid limit
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* upper - Upper valid limit
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*
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****************************************************************************/
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static uint32_t lpc54_emc_timercycles(uint32_t nsec, uint32_t lower,
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uint32_t upper)
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{
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uint32_t cycles;
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cycles = BOARD_EMC_FREQUENCY / MHZ_PER_HZ * nsec;
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return ((cycles + MSEC_PER_SEC - 1) / MSEC_PER_SEC);
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/* Decrease according to the plus */
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if (cycles < lower)
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{
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cycles = lower;
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}
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else if (cycles > upper)
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{
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cycles = upper;
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}
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return cycles;
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}
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/****************************************************************************
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* Name: lpc54_emc_timercycles
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*
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* Description:
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* Get the shift value to shift the mode register content by.
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*
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* Input Parameters:
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* addrmap - EMC address map for the dynamic memory configuration. This is
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* bit 14 ~ bit 7 of the EMC_DYNCONFIG.
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*
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* Returned Value:
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* The offset value to shift the mode register content by.
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*
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****************************************************************************/
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#ifdef CONFIG_LPC54_EMC_DYNAMIC
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static uint32_t lpc54_emc_modeoffset(uint32_t addrmap)
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{
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uint8_t offset = 0;
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uint32_t columbase = addrmap & EMC_DYNCTL_COLUMNBASE_MASK;
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/* First calculate the column length. */
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if (columbase == 0x10)
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{
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offset = 8;
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}
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else
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{
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if (!columbase)
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{
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offset = 9;
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}
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else
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{
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offset = 8;
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}
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/* Add column length increase check. */
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if (((addrmap & EMC_DYNCTL_COLUMNPLUS_MASK) >> EMC_DYNCTL_COLUMNPLUS_SHIFT) == 1)
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{
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offset += 1;
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}
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else if (((addrmap & EMC_DYNCTL_COLUMNPLUS_MASK) >> EMC_DYNCTL_COLUMNPLUS_SHIFT) == 2)
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{
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offset += 2;
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}
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else
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{
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/* To avoid MISRA rule 14.10 error. */
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}
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}
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/* Add Buswidth/16. */
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if (addrmap & EMC_DYNCTL_BUSWIDTH_MASK)
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{
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offset += 2;
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}
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else
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{
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offset += 1;
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}
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/* Add bank select bit if the sdram address map mode is RBC(row-bank-column) mode. */
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if (!(addrmap & EMC_DYNCTL_BUSADDRMAP_MASK))
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{
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if (!(addrmap & EMC_DYNCTL_DEVBANKS_BITS_MASK))
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{
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offset += 1;
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}
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else
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{
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offset += 2;
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}
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}
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return offset;
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}
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#endif /* CONFIG_LPC54_EMC_DYNAMIC */
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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@ -63,10 +224,12 @@
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* This function enables the EMC clock, initializes the emc system
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* configuration, and enable the EMC module.
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*
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* Input Parameters:
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* config - Describes the EMC configuration.
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*
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****************************************************************************/
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void lpc54_emc_initialize(uintptr_t base,
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FAR const struct emc_config_s *config)
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void lpc54_emc_initialize(FAR const struct emc_config_s *config)
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{
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uint32_t regval;
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@ -88,7 +251,7 @@ void lpc54_emc_initialize(uintptr_t base,
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/* Set the endian mode */
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regval = config->endian ? EMC_CONFIG_EM : 0;
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regval = config->bigendian ? EMC_CONFIG_EM : 0;
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putreg32(regval, LPC54_EMC_CONFIG);
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/* Enable the EMC module with normal memory map mode and normal work mode. */
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@ -96,4 +259,202 @@ void lpc54_emc_initialize(uintptr_t base,
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putreg32(EMC_CONTROL_E, LPC54_EMC_CONTROL);
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}
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/****************************************************************************
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* Name: lpc54_emc_sdram_initialize
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*
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* Description:
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* This function initializes the dynamic memory controller in external
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* memory controller. This function must be called after lpc54_emc_initialize
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* and before accessing the external dynamic memory.
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*
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* Input Parameters:
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* timing - The timing and latency for dynamica memory controller
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* setting. It will be used for all dynamic memory chips,
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* therefore the worst timing value for all used chips must be
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* given.
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* chconfig - The EMC dynamic memory controller chip-independent
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* configuration array. The dimension of the array is given by
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* nchips.
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* nchips - The number of chips to configure and the dimension of the
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* chconfig array.
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*
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****************************************************************************/
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#ifdef CONFIG_LPC54_EMC_DYNAMIC
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void lpc54_emc_sdram_initialize(FAR struct emc_dynamic_timing_config_s *timing,
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FAR struct emc_dynamic_chip_config_s *chconfig,
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unsigned int nchips)
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{
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FAR struct emc_dynamic_chip_config_s *config;
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uintptr_t addr;
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uint32_t regval;
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uint32_t offset;
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uint32_t data;
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unsigned int i;
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volatile unsigned int j;
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/* Setting for dynamic memory controller chip independent configuration */
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for (i = 0, config = chconfig;
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i < nchips && config != NULL;
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i++, config++)
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{
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uint8_t caslat;
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regval = EMC_DYNCONFIG_MD(config->dyndev) |
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EMC_DYNCONFIG_ADDRMAP(config->addrmap);
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putreg32(regval, LPC54_EMC_DYNCONFIG(config->chndx));
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/* Abstract CAS latency from the SDRAM mode reigster setting values */
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caslat = (config->mode & EMC_SDRAM_MODE_CL_MASK) >> EMC_SDRAM_MODE_CL_SHIFT;
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regval = EMC_DYNRASCAS_RAS(config->rasnclk) | EMC_DYNRASCAS_CAS(caslat);
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putreg32(regval, LPC54_EMC_DYNRASCAS(config->chndx));
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}
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/* Configure the Dynamic Memory controller timing/latency for all chips. */
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regval = EMC_DYNREADCONFIG(timing->rdconfig);
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putreg32(regval, LPC54_EMC_DYNREADCONFIG);
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regval = lpc54_emc_timercycles(timing->rp, 1, 16);
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putreg32(EMC_DYNRP(regval), LPC54_EMC_DYNRP);
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||||
regval = lpc54_emc_timercycles(timing->ras, 1, 16);
|
||||
putreg32(EMC_DYNRAS(regval), LPC54_EMC_DYNRAS);
|
||||
|
||||
regval = lpc54_emc_timercycles(timing->srex, 1, 16);
|
||||
putreg32(EMC_DYNSREX(regval), LPC54_EMC_DYNSREX);
|
||||
|
||||
regval = lpc54_emc_timercycles(timing->apr, 1, 16);
|
||||
putreg32(EMC_DYNAPR(regval), LPC54_EMC_DYNAPR);
|
||||
|
||||
regval = lpc54_emc_timercycles(timing->dal, 0, 15);
|
||||
putreg32(EMC_DYNDAL(regval), LPC54_EMC_DYNDAL);
|
||||
|
||||
regval = lpc54_emc_timercycles(timing->wr, 1, 16);
|
||||
putreg32(EMC_DYNWR(regval), LPC54_EMC_DYNWR);
|
||||
|
||||
regval = lpc54_emc_timercycles(timing->rc, 1, 32);
|
||||
putreg32(EMC_DYNRC(regval), LPC54_EMC_DYNRC);
|
||||
|
||||
regval = lpc54_emc_timercycles(timing->rfc, 1, 32);
|
||||
putreg32(EMC_DYNRFC(regval), LPC54_EMC_DYNRFC);
|
||||
|
||||
regval = lpc54_emc_timercycles(timing->xsr, 1, 32);
|
||||
putreg32(EMC_DYNXSR(regval), LPC54_EMC_DYNXSR);
|
||||
|
||||
regval = lpc54_emc_timercycles(timing->rrd, 1, 16);
|
||||
putreg32(EMC_DYNRRD(regval), LPC54_EMC_DYNRRD);
|
||||
|
||||
regval = EMC_DYNRRD(timing->mrd);
|
||||
putreg32(regval, LPC54_EMC_DYNMRD);
|
||||
|
||||
/* Initialize the SDRAM.*/
|
||||
|
||||
for (j = 0; j < EMC_SDRAM_WAIT_CYCLES; j++)
|
||||
{
|
||||
}
|
||||
|
||||
/* Step 2. Issue NOP command. */
|
||||
|
||||
regval = EMC_DYNCONTROL_CE | EMC_DYNCONTROL_CS | EMC_DYNCONTROL_I_MODE;
|
||||
putreg32(regval, LPC54_EMC_DYNCONTROL);
|
||||
|
||||
for (j = 0; j < EMC_SDRAM_WAIT_CYCLES; j++)
|
||||
{
|
||||
}
|
||||
|
||||
/* Step 3. Issue precharge all command. */
|
||||
|
||||
regval = EMC_DYNCONTROL_CE | EMC_DYNCONTROL_CS | EMC_DYNCONTROL_I_PALL;
|
||||
putreg32(regval, LPC54_EMC_DYNCONTROL);
|
||||
|
||||
/* Step 4. Issue two auto-refresh command. */
|
||||
|
||||
putreg32(2 * EMC_REFRESH_CLOCK_SCALE, LPC54_EMC_DYNREFRESH);
|
||||
|
||||
for (i = 0; i < EMC_SDRAM_WAIT_CYCLES/2; i ++)
|
||||
{
|
||||
}
|
||||
|
||||
regval = lpc54_emc_timercycles(timing->refresh, 0,
|
||||
EMC_REFRESH_CLOCK_SCALE * 2047);
|
||||
putreg32(regval / EMC_REFRESH_CLOCK_SCALE, LPC54_EMC_DYNREFRESH);
|
||||
|
||||
/* Step 5. Issue a mode command and set the mode value. */
|
||||
|
||||
regval = EMC_DYNCONTROL_CE | EMC_DYNCONTROL_CS | EMC_DYNCONTROL_I_MODE;
|
||||
putreg32(regval, LPC54_EMC_DYNCONTROL);
|
||||
|
||||
/* Calculate the mode settings here and to reach the 8 auto-refresh time
|
||||
* requirement.
|
||||
*/
|
||||
|
||||
for (i = 0, config = chconfig;
|
||||
i < nchips && config != NULL;
|
||||
i++, config++)
|
||||
{
|
||||
/* Get the shift value first. */
|
||||
|
||||
offset = lpc54_emc_modeoffset(config->addrmap);
|
||||
addr = g_dram_csbase[config->chndx] |
|
||||
((uint32_t)(config->mode & ~EMC_SDRAM_BANKCS_BA_MASK ) << offset);
|
||||
|
||||
/* Set the right mode setting value. */
|
||||
|
||||
data = *(volatile uint32_t *)addr;
|
||||
data = data;
|
||||
}
|
||||
|
||||
if (config->dyndev)
|
||||
{
|
||||
/* Add extended mode register if the low-power sdram is used. */
|
||||
|
||||
regval = EMC_DYNCONTROL_CE | EMC_DYNCONTROL_CS |
|
||||
EMC_DYNCONTROL_I_MODE;
|
||||
putreg32(regval, LPC54_EMC_DYNCONTROL);
|
||||
|
||||
/* Calculate the mode settings for extended mode register. */
|
||||
|
||||
for (i = 0, config = chconfig;
|
||||
i < nchips && config != NULL;
|
||||
i++, config++)
|
||||
{
|
||||
/* Get the shift value first. */
|
||||
|
||||
offset = lpc54_emc_modeoffset(config->addrmap);
|
||||
addr = (g_dram_csbase[config->chndx] |
|
||||
(((uint32_t)(config->extmode & ~EMC_SDRAM_BANKCS_BA_MASK) |
|
||||
EMC_SDRAM_BANKCS_BA1_MASK) << offset));
|
||||
|
||||
/* Set the right mode setting value. */
|
||||
|
||||
data = *(volatile uint32_t *)addr;
|
||||
data = data;
|
||||
}
|
||||
}
|
||||
|
||||
/* Step 6. Issue normal operation command. */
|
||||
|
||||
regval = EMC_DYNCONTROL_I_NORMAL;
|
||||
putreg32(regval, LPC54_EMC_DYNCONTROL);
|
||||
|
||||
/* The buffer will be disabled when do the sdram initialization and
|
||||
* enabled after the initialization during normal opeation.
|
||||
*/
|
||||
|
||||
for (i = 0, config = chconfig;
|
||||
i < nchips && config != NULL;
|
||||
i++, config++)
|
||||
{
|
||||
uintptr_t regaddr = LPC54_EMC_DYNCONFIG(config->chndx);
|
||||
|
||||
regval = getreg32(regaddr);
|
||||
regval |= EMC_DYNCONFIG_B;
|
||||
putreg32(regval, regaddr);
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_LPC54_EMC_DYNAMIC */
|
||||
|
||||
#endif /* CONFIG_LPC54_EMC */
|
||||
|
||||
@ -47,6 +47,10 @@
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "lpc54_config.h"
|
||||
|
||||
#ifdef CONFIG_LPC54_EMC
|
||||
@ -57,7 +61,7 @@
|
||||
|
||||
/* EMC Feedback clock input source selection */
|
||||
|
||||
enum _emc_fbclk_src_e
|
||||
enum emc_fbclksrc_e
|
||||
{
|
||||
EMC_INTLOOPBACK = 0, /* Use the internal loop back from EMC_CLK output */
|
||||
EMC_FBCLLK /* Use the external EMC_FBCLK input */
|
||||
@ -72,6 +76,67 @@ struct emc_config_s
|
||||
uint8_t clkdiv; /* EMC_CLK = AHB_CLK / (emc_clkDiv + 1). */
|
||||
};
|
||||
|
||||
/* EMC dynamic read strategy. */
|
||||
|
||||
enum emc_dynamic_read_e
|
||||
{
|
||||
EMC_NODELAY = 0, /* No delay */
|
||||
EMC_CMDDELAY, /* Command delayed strategy, using EMCCLKDELAY */
|
||||
EMC_CMDDELAYPLUS1, /* Command delayed strategy pluse one clock cycle
|
||||
* using EMCCLKDELAY */
|
||||
EMC_CMDDELAYPLUS2, /* Command delayed strategy pulse two clock cycle
|
||||
* using EMCCLKDELAY */
|
||||
};
|
||||
|
||||
/* EMC dynamic timing/delay configure structure. */
|
||||
|
||||
struct emc_dynamic_timing_config_s
|
||||
{
|
||||
uint8_t rdconfig; /* Dynamic read strategy (see enum emc_dynamic_read_e) */
|
||||
uint32_t refresh; /* The refresh period in units of nanoseconds */
|
||||
uint32_t rp; /* Precharge command period in units of nanoseconds */
|
||||
uint32_t ras; /* Active to precharge command period in units of
|
||||
* nanoseconds */
|
||||
uint32_t srex; /* Self-refresh exit time in units of nanoseconds */
|
||||
uint32_t apr; /* Last data out to active command time in units of
|
||||
* nanoseconds */
|
||||
uint32_t dal; /* Data-in to active command in units of nanoseconds */
|
||||
uint32_t wr; /* Write recovery time in unit of nanosecond */
|
||||
uint32_t rc; /* Active to active command period in units of
|
||||
* nanoseconds. */
|
||||
uint32_t rfc; /* Auto-refresh period and auto-refresh to active
|
||||
* command period in unit of nanosecond */
|
||||
uint32_t xsr; /* Exit self-refresh to active command time in units
|
||||
* of nanoseconds */
|
||||
uint32_t rrd; /* Active bank A to active bank B latency in units of
|
||||
* nanoseconds */
|
||||
uint8_t mrd; /* Load mode register to active command time in units
|
||||
* of EMCCLK cycles */
|
||||
};
|
||||
|
||||
/* EMC dynamic memory device. */
|
||||
|
||||
enum emc_dynamic_device_e
|
||||
{
|
||||
EMC_SDRAM = 0, /* Dynamic memory device: SDRAM. */
|
||||
EMC_LPSDRAM /* Dynamic memory device: Low-power SDRAM. */
|
||||
};
|
||||
|
||||
/* EMC dynamic memory controller independent chip configuration structure */
|
||||
|
||||
struct emc_dynamic_chip_config_s
|
||||
{
|
||||
uint8_t chndx; /* Chip Index, range from 0 ~ EMC_DYNAMIC_MEMDEV_NUM - 1. */
|
||||
uint8_t dyndev; /* All chips shall use the same device setting. mixed
|
||||
* use are not supported. */
|
||||
uint8_t rasnclk; /* Active to read/write delay tRCD. */
|
||||
uint16_t mode; /* Sdram mode register setting. */
|
||||
uint16_t extmode; /* Used for low-power sdram device. The extended mode
|
||||
* register. */
|
||||
uint8_t addrmap; /* Dynamic device address mapping, choose the address
|
||||
* mapping for your specific device. */
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
@ -83,10 +148,39 @@ struct emc_config_s
|
||||
* This function enables the EMC clock, initializes the emc system
|
||||
* configuration, and enable the EMC module.
|
||||
*
|
||||
* Input Parameters:
|
||||
* config - Describes the EMC configuration.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void lpc54_emc_initialize(uintptr_t base,
|
||||
FAR const struct emc_config_s *config);
|
||||
void lpc54_emc_initialize(FAR const struct emc_config_s *config);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc54_emc_sdram_initialize
|
||||
*
|
||||
* Description:
|
||||
* This function initializes the dynamic memory controller in external
|
||||
* memory controller. This function must be called after lpc54_emc_initialize
|
||||
* and before accessing the external dynamic memory.
|
||||
*
|
||||
* Input Parameters:
|
||||
* timing - The timing and latency for dynamica memory controller
|
||||
* setting. It will be used for all dynamic memory chips,
|
||||
* therefore the worst timing value for all used chips must be
|
||||
* given.
|
||||
* chconfig - The EMC dynamic memory controller chip-independent
|
||||
* configuration array. The dimension of the array is given by
|
||||
* nchips.
|
||||
* nchips - The number of chips to configure and the dimension of the
|
||||
* chconfig array.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_LPC54_EMC_DYNAMIC
|
||||
void lpc54_emc_sdram_initialize(FAR struct emc_dynamic_timing_config_s *timing,
|
||||
FAR struct emc_dynamic_chip_config_s *chconfig,
|
||||
unsigned int nchips);
|
||||
#endif /* CONFIG_LPC54_EMC_DYNAMIC */
|
||||
|
||||
#endif /* CONFIG_LPC54_EMC */
|
||||
#endif /* __ARCH_ARM_SRC_LPC54XX_LPC54_EMC_H */
|
||||
|
||||
@ -178,6 +178,15 @@
|
||||
#define BOARD_FLEXCOMM0_CLKSEL SYSCON_FCLKSEL_FRO12M
|
||||
#define BOARD_FLEXCOMM0_FCLK LPC54_FRO_12MHZ
|
||||
|
||||
/* EMC */
|
||||
|
||||
#ifdef BOARD_220MHz
|
||||
#define BOARD_EMC_CLKDIV 3 /* EMC Clock = CPU FREQ/3 */
|
||||
#else /* if BOARD_180MHz */
|
||||
#define BOARD_EMC_CLKDIV 2 /* EMC Clock = CPU FREQ/2 */
|
||||
#endif
|
||||
#define BOARD_EMC_FREQUENCY (BOARD_CPU_FREQUENCY / BOARD_EMC_CLKDIV)
|
||||
|
||||
/* LED definitions *********************************************************/
|
||||
/* The LPCXpress-LPC54628 has three user LEDs: D9, D11, and D12. These
|
||||
* LEDs are for application use. They are illuminated when the driving
|
||||
|
||||
@ -13,6 +13,8 @@ CONFIG_FAT_LCNAMES=y
|
||||
CONFIG_FAT_LFN=y
|
||||
CONFIG_FS_FAT=y
|
||||
CONFIG_FS_PROCFS=y
|
||||
CONFIG_LPC54_EMC_DYNAMIC=y
|
||||
CONFIG_LPC54_EMC=y
|
||||
CONFIG_LPC54_USART0=y
|
||||
CONFIG_MAX_TASKS=16
|
||||
CONFIG_MAX_WDOGPARMS=2
|
||||
|
||||
@ -46,4 +46,10 @@ ifeq ($(CONFIG_LIB_BOARDCTL),y)
|
||||
CSRCS += lpc54_appinit.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_LPC54_EMC),y)
|
||||
ifeq ($(CONFIG_LPC54_EMC_DYNAMIC),y)
|
||||
CSRCS += lpc54_sdram.c
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(TOPDIR)/configs/Board.mk
|
||||
|
||||
@ -44,7 +44,13 @@
|
||||
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#ifdef CONFIG_LPC54_EMC
|
||||
#if defined(CONFIG_LPC54_EMC) && defined(CONFIG_LPC54_EMC_DYNAMIC)
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define EMC_CLOCK_PERIOD_NS (1000000000 / BOARD_EMC_FREQUENCY)
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
@ -63,6 +69,37 @@ static const struct emc_config_s g_emc_config =
|
||||
#endif
|
||||
};
|
||||
|
||||
/* Dynamic memory timing configuration. */
|
||||
|
||||
static const struct emc_dynamic_timing_config_s g_emc_dynconfig =
|
||||
{
|
||||
.rdconfig = EMC_CMDDELAY;
|
||||
.refresh = (64 * 1000000 / 4096) /* 4096 rows/ 64ms */;
|
||||
.rp = 18;
|
||||
.ras = 42;
|
||||
.srex = 67;
|
||||
.apr = 18;
|
||||
.wr = EMC_CLOCK_PERIOD_NS + 6; /* one clk + 6ns */
|
||||
.dal = EMC_CLOCK_PERIOD_NS + 24;
|
||||
.rc = 60;
|
||||
.rfc = 60;
|
||||
.xsr = 67;
|
||||
.rrd = 23;
|
||||
.mrd = 2;
|
||||
};
|
||||
|
||||
/* Dynamic memory chip specific configuration: Chip 0 - MTL48LC8M16A2B4-6A */
|
||||
|
||||
static onst struct emc_dynamic_chip_config_s g_emc_dynchipconfig;
|
||||
{
|
||||
.chndx = 0;
|
||||
.dyndev = EMC_SDRAM;
|
||||
.rasnclk = 2;
|
||||
.mode = 0x23;
|
||||
.extmode = 0; /* LPSDRAM only */
|
||||
.addrmap = 0x09; /* 128Mbits (8M*16, 4banks, 12 rows, 9 columns)*/
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
@ -77,18 +114,13 @@ static const struct emc_config_s g_emc_config =
|
||||
|
||||
void lpc54_sdram_initialize(void)
|
||||
{
|
||||
/* Dynamic memory timing configuration. */
|
||||
#warning Missing logic
|
||||
|
||||
/* Dynamic memory chip specific configuration: Chip 0 - MTL48LC8M16A2B4-6A */
|
||||
#warning Missing logic
|
||||
|
||||
/* EMC Basic configuration. */
|
||||
|
||||
lpc54_emc_initialize(EMC, &g_emc_config);
|
||||
lpc54_emc_initialize(&g_emc_config);
|
||||
|
||||
/* EMC Dynamc memory configuration. */
|
||||
#warning Missing logic
|
||||
|
||||
lpc54_emc_dram_initialize(&g_emc_dynconfig, &g_emc_dynchipconfig, 1);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_LPC54_EMC */
|
||||
#endif /* CONFIG_LPC54_EMC && CONFIG_LPC54_EMC_DYNAMIC */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user