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boards/risc-v/litex/arty_a7: update README to include building in LITESDCARD peripheral

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Richard Tucker 2022-03-24 15:41:01 +11:00 committed by Xiang Xiao
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boards/risc-v/litex/arty_a7/README.txt
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@ -5,6 +5,9 @@
2. Follow instruction on https://github.com/enjoy-digital/litex to build the vexriscv softcore fpga gateware
and flash to arty_a7 board
$ cd litex-boards/litex_boards/targets
$ ./digilent_arty.py --with-sdcard --uart-baudrate 1000000 --cpu-type=vexriscv --cpu-variant=secure --build --load --flash
3. Configure and build NuttX
$ mkdir ./nuttx; cd ./nuttx