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add efm32_gpioirqclear

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This commit is contained in:
pnb 2015-09-05 10:20:24 +02:00
parent ed8531a53b
commit ea596e45d3
2 changed files with 42 additions and 0 deletions
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14
arch/arm/src/efm32/efm32_gpio.h
View File

@ -328,6 +328,20 @@ void efm32_gpioirqdisable(int irq);
# define efm32_gpioirqdisable(irq)
#endif
/************************************************************************************
* Name: efm32_gpioirqclear
*
* Description:
* clear the interrupt for specified PIO IRQ
*
************************************************************************************/
#ifdef CONFIG_EFM32_GPIO_IRQ
void efm32_gpioirqclear(int irq);
#else
# define efm32_gpioirqclear(irq)
#endif
/************************************************************************************
* Function: efm32_dumpgpio
*

28
arch/arm/src/efm32/efm32_gpioirq.c
View File

@ -314,4 +314,32 @@ void efm32_gpioirqdisable(int irq)
}
}
/************************************************************************************
* Name: efm32_gpioirqclear
*
* Description:
* Disable the interrupt for specified PIO IRQ
*
************************************************************************************/
void efm32_gpioirqclear(int irq)
{
irqstate_t flags;
uint32_t regval;
uint32_t bit;
if (irq >= EFM32_IRQ_EXTI0 && irq <= EFM32_IRQ_EXTI15)
{
/* Enable the interrupt associated with the pin */
bit = ((uint32_t)1 << (irq - EFM32_IRQ_EXTI0));
flags = irqsave();
regval = getreg32(EFM32_GPIO_IFC);
regval |= bit;
putreg32(regval, EFM32_GPIO_IFC);
irqrestore(flags);
}
}
#endif /* CONFIG_EFM32_GPIO_IRQ */