ARMv7-A: Cosmetic changes
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@ -1,5 +1,5 @@
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/****************************************************************************
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* arch/arm/src/armv7/up_coherent_dcache.c
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* arch/arm/src/armv7-a/up_coherent_dcache.c
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*
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* Copyright (C) 2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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@ -54,10 +54,13 @@
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* Configuration
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**********************************************************************************/
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#undef ALIGNMENT_TRAP
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/* Hard-coded options */
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#undef CPU_ALIGNMENT_TRAP
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#undef CPU_CACHE_ROUND_ROBIN
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#undef CPU_DCACHE_DISABLE
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#undef CPU_ICACHE_DISABLE
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#undef CPU_AFE_ENABLE
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/* There are three operational memory configurations:
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*
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@ -465,7 +468,7 @@ __start:
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orr r0, r0, #(SCTLR_I)
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#endif
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#ifdef ALIGNMENT_TRAP
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#ifdef CPU_ALIGNMENT_TRAP
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/* Alignment abort enable
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*
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* SCTLR_A Bit 1: Strict alignment enabled
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@ -474,7 +477,7 @@ __start:
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orr r0, r0, #(SCTLR_A)
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#endif
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#ifdef CONFIG_AFE_ENABLE
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#ifdef CPU_AFE_ENABLE
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/* AP[0:2] Permissions model
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*
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* SCTLR_AFE Bit 29: Full, legacy access permissions behavior (reset value).
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@ -461,7 +461,7 @@ __start:
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orr r0, r0, #(SCTLR_A)
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#endif
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#ifdef CONFIG_AFE_ENABLE
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#ifdef CPU_AFE_ENABLE
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/* AP[0:2] Permissions model
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*
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* SCTLR_AFE Bit 29: Full, legacy access permissions behavior (reset value).
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@ -1,5 +1,5 @@
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/****************************************************************************
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* arch/arm/src/armv7/arm_undefinedinsn.c
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* arch/arm/src/armv7-a/arm_undefinedinsn.c
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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@ -1,6 +1,5 @@
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/****************************************************************************
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* arch/arm/src/armv7-a/l2cc.h
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* Non-CP15 Registers
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*
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* Copyright (C) 2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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@ -342,7 +342,7 @@
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* PL2 - Software executing in Hyp mode
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*/
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#ifdef CONFIG_AFE_ENABLE
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#ifdef CPU_AFE_ENABLE
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/* AP[2:1] access permissions model. AP[0] is used as an access flag:
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*
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* AP[2] AP[1] PL1 PL0 Description
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