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arch/arm/src/imxrt/chip: Add some missing definitions for GPIO5

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This commit is contained in:
Gregory Nutt 2018-04-25 15:12:08 -06:00
parent 17cc0b9bfe
commit f3a8e01557
2 changed files with 11 additions and 0 deletions
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9
arch/arm/src/imxrt/chip/imxrt_gpio.h
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@ -105,6 +105,15 @@
#define IMXRT_GPIO4_ISR (IMXRT_GPIO4_BASE + IMXRT_GPIO_ISR_OFFSET) #define IMXRT_GPIO4_ISR (IMXRT_GPIO4_BASE + IMXRT_GPIO_ISR_OFFSET)
#define IMXRT_GPIO4_EDGE (IMXRT_GPIO4_BASE + IMXRT_GPIO_EDGE_OFFSET) #define IMXRT_GPIO4_EDGE (IMXRT_GPIO4_BASE + IMXRT_GPIO_EDGE_OFFSET)
#define IMXRT_GPIO5_DR (IMXRT_GPIO5_BASE + IMXRT_GPIO_DR_OFFSET)
#define IMXRT_GPIO5_GDIR (IMXRT_GPIO5_BASE + IMXRT_GPIO_GDIR_OFFSET)
#define IMXRT_GPIO5_PSR (IMXRT_GPIO5_BASE + IMXRT_GPIO_PSR_OFFSET)
#define IMXRT_GPIO5_ICR1 (IMXRT_GPIO5_BASE + IMXRT_GPIO_ICR1_OFFSET)
#define IMXRT_GPIO5_ICR2 (IMXRT_GPIO5_BASE + IMXRT_GPIO_ICR2_OFFSET)
#define IMXRT_GPIO5_IMR (IMXRT_GPIO5_BASE + IMXRT_GPIO_IMR_OFFSET)
#define IMXRT_GPIO5_ISR (IMXRT_GPIO5_BASE + IMXRT_GPIO_ISR_OFFSET)
#define IMXRT_GPIO5_EDGE (IMXRT_GPIO5_BASE + IMXRT_GPIO_EDGE_OFFSET)
/* Register bit definitions *****************************************************************/ /* Register bit definitions *****************************************************************/
/* Most registers are laid out simply with one bit per pin */ /* Most registers are laid out simply with one bit per pin */

2
arch/arm/src/imxrt/chip/imxrt_iomuxc.h
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@ -1296,6 +1296,7 @@
#define GPR_GPR2_QTIM4_TMR_RESET (1 << 31) #define GPR_GPR2_QTIM4_TMR_RESET (1 << 31)
/* General Purpose Register 3 (GPR3) */ /* General Purpose Register 3 (GPR3) */
#define GPR_GPR3_OCRAM_CTL_SHIFT (0) #define GPR_GPR3_OCRAM_CTL_SHIFT (0)
#define GPR_GPR3_OCRAM_CTL_MASK (15 << GPR_GPR3_OCRAM_CTL_SHIFT) #define GPR_GPR3_OCRAM_CTL_MASK (15 << GPR_GPR3_OCRAM_CTL_SHIFT)
# define GPR_GPR3_OCRAM_CTL_READ_DATA_PIPELINE_EN (1 << GPR_GPR3_OCRAM_CTL_SHIFT) # define GPR_GPR3_OCRAM_CTL_READ_DATA_PIPELINE_EN (1 << GPR_GPR3_OCRAM_CTL_SHIFT)
@ -1321,6 +1322,7 @@
#define GPR_GPR4_FLEXIO2_STOP_REQ (1 << 13) #define GPR_GPR4_FLEXIO2_STOP_REQ (1 << 13)
/* General Purpose Register 5 (GPR5) */ /* General Purpose Register 5 (GPR5) */
#define GPR_GPR5_WDOG1_MASK (1 << 6) #define GPR_GPR5_WDOG1_MASK (1 << 6)
#define GPR_GPR5_WDOG2_MASK (1 << 7) #define GPR_GPR5_WDOG2_MASK (1 << 7)
#define GPR_GPR5_GPT2_CAPIN1_SEL_PAD (0 << 23) #define GPR_GPR5_GPT2_CAPIN1_SEL_PAD (0 << 23)