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SAML21: Several SERCOM fixes. No gets UART output, but at the wrong BAUD

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This commit is contained in:
Gregory Nutt 2015-05-23 13:08:28 -06:00
parent 7b7da5ded4
commit fa585b66a3
5 changed files with 22 additions and 16 deletions
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2
arch/arm/src/samdl/chip/saml_gclk.h
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@ -56,7 +56,7 @@
/* GCLK register offsets ********************************************************************/ /* GCLK register offsets ********************************************************************/
#define SAM_GCLK_CTRLA_OFFSET 0x0000 /* Control register */ #define SAM_GCLK_CTRLA_OFFSET 0x0000 /* Control register */
#define SAM_GCLK_SYNCHBUSY_OFFSET 0x0004 /* Status register */ #define SAM_GCLK_SYNCHBUSY_OFFSET 0x0004 /* Status register */
#define SAM_GCLK_GENCTRL_OFFSET(n) (0x0020 + ((n) << 2)) /* General clock generator n */ #define SAM_GCLK_GENCTRL_OFFSET(n) (0x0020 + ((n) << 2)) /* General clock generator n */
#define SAM_GCLK_PCHCTRL_OFFSET(m) (0x0080 + ((m) << 2)) /* Peripheral channel control m */ #define SAM_GCLK_PCHCTRL_OFFSET(m) (0x0080 + ((m) << 2)) /* Peripheral channel control m */

12
arch/arm/src/samdl/chip/saml_usart.h
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@ -65,7 +65,7 @@
#define SAM_USART_INTFLAG_OFFSET 0x0018 /* Interrupt flag and status clear register */ #define SAM_USART_INTFLAG_OFFSET 0x0018 /* Interrupt flag and status clear register */
#define SAM_USART_STATUS_OFFSET 0x001a /* Status register */ #define SAM_USART_STATUS_OFFSET 0x001a /* Status register */
#define SAM_USART_SYNCBUSY_OFFSET 0x001c /* Synchronization busy register */ #define SAM_USART_SYNCBUSY_OFFSET 0x001c /* Synchronization busy register */
#define SAM_USART_DATA_OFFSET 0x0018 /* Data register */ #define SAM_USART_DATA_OFFSET 0x0028 /* Data register */
#define SAM_USART_DBGCTRL_OFFSET 0x0030 /* Debug control register */ #define SAM_USART_DBGCTRL_OFFSET 0x0030 /* Debug control register */
/* USART register addresses *****************************************************************/ /* USART register addresses *****************************************************************/
@ -156,11 +156,11 @@
#define USART_CTRLA_IBON (1 << 8) /* Bit 8: Immediate BUFOVF notification */ #define USART_CTRLA_IBON (1 << 8) /* Bit 8: Immediate BUFOVF notification */
#define USART_CTRLA_SAMPR_SHIFT (11) /* Bits 11-12: Sample rate */ #define USART_CTRLA_SAMPR_SHIFT (11) /* Bits 11-12: Sample rate */
#define USART_CTRLA_SAMPR_MASK (3 << USART_CTRLA_SAMPR_SHIFT) #define USART_CTRLA_SAMPR_MASK (3 << USART_CTRLA_SAMPR_SHIFT)
# define USART_CTRLA_SAMPR_16XA (xx << USART_CTRLA_SAMPR_SHIFT) /* 16x oversampling; arithmetic baud */ # define USART_CTRLA_SAMPR_16XA (0 << USART_CTRLA_SAMPR_SHIFT) /* 16x oversampling; arithmetic baud */
# define USART_CTRLA_SAMPR_16XF (xx << USART_CTRLA_SAMPR_SHIFT) /* 16x oversampling; fractional baud */ # define USART_CTRLA_SAMPR_16XF (1 << USART_CTRLA_SAMPR_SHIFT) /* 16x oversampling; fractional baud */
# define USART_CTRLA_SAMPR_8XA (xx << USART_CTRLA_SAMPR_SHIFT) /* 8x oversampling; arithmetic baud */ # define USART_CTRLA_SAMPR_8XA (2 << USART_CTRLA_SAMPR_SHIFT) /* 8x oversampling; arithmetic baud */
# define USART_CTRLA_SAMPR_8XF (xx << USART_CTRLA_SAMPR_SHIFT) /* 8x oversampling; fractional baud */ # define USART_CTRLA_SAMPR_8XF (3 << USART_CTRLA_SAMPR_SHIFT) /* 8x oversampling; fractional baud */
# define USART_CTRLA_SAMPR_3XA (xx << USART_CTRLA_SAMPR_SHIFT) /* 3x oversampling; arithmetic baud */ # define USART_CTRLA_SAMPR_3XA (4 << USART_CTRLA_SAMPR_SHIFT) /* 3x oversampling; arithmetic baud */
#define USART_CTRLA_TXPO_SHIFT (16) /* Bits 16-17: Transmit data pinout */ #define USART_CTRLA_TXPO_SHIFT (16) /* Bits 16-17: Transmit data pinout */
#define USART_CTRLA_TXPO_MASK (3 << USART_CTRLA_TXPO_SHIFT) #define USART_CTRLA_TXPO_MASK (3 << USART_CTRLA_TXPO_SHIFT)
# define USART_CTRLA_TXPAD0_1 (0 << USART_CTRLA_TXPO_SHIFT) /* TxD=SERCOM PAD[0]; XCK=PAD[1] */ # define USART_CTRLA_TXPAD0_1 (0 << USART_CTRLA_TXPO_SHIFT) /* TxD=SERCOM PAD[0]; XCK=PAD[1] */

3
arch/arm/src/samdl/sam_lowputc.c
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@ -132,6 +132,9 @@ sam_usart_configure(const struct sam_usart_config_s * const config)
* *
* BAUD = 63,019 * BAUD = 63,019
* Fbaud = 115,219 * Fbaud = 115,219
*
* REVISIT: For the SAML21, only 16x sampling with arithmetic BAUD is
* supported.
*/ */
tmp = (uint64_t)config->baud << 20; tmp = (uint64_t)config->baud << 20;

9
arch/arm/src/samdl/sam_sercom.c
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@ -45,6 +45,7 @@
#include <stdint.h> #include <stdint.h>
#include <stdbool.h> #include <stdbool.h>
#include <assert.h>
#include "up_arch.h" #include "up_arch.h"
@ -54,6 +55,8 @@
#include "sam_gclk.h" #include "sam_gclk.h"
#include "sam_sercom.h" #include "sam_sercom.h"
#include <arch/board/board.h>
/**************************************************************************** /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
****************************************************************************/ ****************************************************************************/
@ -145,7 +148,7 @@ void sercom_coreclk_configure(int sercom, int gclkgen, bool wrlock)
void sercom_slowclk_configure(int gclkgen) void sercom_slowclk_configure(int gclkgen)
{ {
#if defined(CONFIG_ARCH_FAMILY_SAMDL21) #if defined(CONFIG_ARCH_FAMILY_SAML21)
static bool configured = false; static bool configured = false;
#ifdef CONFIG_DEBUG #ifdef CONFIG_DEBUG
static uint8_t slowgen = 0xff; static uint8_t slowgen = 0xff;
@ -165,7 +168,7 @@ void sercom_slowclk_configure(int gclkgen)
configured = true; configured = true;
#ifdef CONFIG_DEBUG #ifdef CONFIG_DEBUG
slowgen = (uint8_t)clkgen; slowgen = (uint8_t)gclkgen;
#endif #endif
} }
@ -176,7 +179,7 @@ void sercom_slowclk_configure(int gclkgen)
else else
{ {
DEBUGASSERT((int)slowgen == clkgen); DEBUGASSERT((int)slowgen == gclkgen);
} }
#endif #endif

12
configs/saml21-xplained/include/board.h
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@ -306,7 +306,7 @@
#define BOARD_GCLK2_CLOCK_SOURCE GCLK_GENCTRL_SRC_OSC32K #define BOARD_GCLK2_CLOCK_SOURCE GCLK_GENCTRL_SRC_OSC32K
#define BOARD_GCLK2_PRESCALER 32 #define BOARD_GCLK2_PRESCALER 32
#undef BOARD_GCLK2_OUTPUT_ENABLE #undef BOARD_GCLK2_OUTPUT_ENABLE
#define BOARD_GCLK2_FREQUENCY (BOARD_OSC16M_FREQUENCY / BOARD_GCLK2_PRESCALER) #define BOARD_GCLK2_FREQUENCY (BOARD_OSC32K_FREQUENCY / BOARD_GCLK2_PRESCALER)
/* Configure GCLK generator 3 */ /* Configure GCLK generator 3 */
@ -485,11 +485,11 @@
#define BOARD_SERCOM4_GCLKGEN 0 #define BOARD_SERCOM4_GCLKGEN 0
#define BOARD_SERCOM4_MUXCONFIG (USART_CTRLA_RXPAD1 | USART_CTRLA_TXPAD0_2) #define BOARD_SERCOM4_MUXCONFIG (USART_CTRLA_RXPAD1 | USART_CTRLA_TXPAD0_2)
#define BOARD_SERCOM4_PINMAP_PAD0 PORT_SERCOM4_PAD0_3 /* USART TX */ #define BOARD_SERCOM4_PINMAP_PAD0 PORT_SERCOM4_PAD0_3 /* USART TX */
#define BOARD_SERCOM4_PINMAP_PAD1 PORT_SERCOM4_PAD1_3 /* USART RX */ #define BOARD_SERCOM4_PINMAP_PAD1 PORT_SERCOM4_PAD1_3 /* USART RX */
#define BOARD_SERCOM4_PINMAP_PAD2 0 #define BOARD_SERCOM4_PINMAP_PAD2 0
#define BOARD_SERCOM4_PINMAP_PAD3 0 #define BOARD_SERCOM4_PINMAP_PAD3 0
#define BOARD_SERCOM4_FREQUENCY BOARD_GCLK0_FREQUENCY #define BOARD_SERCOM4_FREQUENCY BOARD_GCLK0_FREQUENCY