Commit Graph

10 Commits

Author SHA1 Message Date
yangshuyong
a537ecdd0f Support nuttx pci endpoint driver framework
Signed-off-by: yangshuyong <yangshuyong@xiaomi.com>
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-09-23 10:03:54 +02:00
p-szafonimateusz
a0e00b993a intel64: register PCI controller early but postpone PCI drivers init
Some of PCI drivers require OS interfaces that can't be executed in the INIT context.
In that case we have to postpone PCI drivers probing and call it for example
in board initialization logic.

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-09-15 03:37:58 +08:00
Bowen Wang
7a495fabb6 pci/pci_uio_ivshmem: pci uio ivshmem msix interrupt support
1. Change pci uio ivshmem driver from pci bus based tp pci-ivshmem
bus based;
2. Add the interrupt support by usin the pci_ivshmem API;

Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
2024-09-14 08:39:52 +08:00
p-szafonimateusz
db6d0bd356 drivers/pci: add MSI/MSI-X support
Add support for MSI and MSI-X in PCI framework

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-09-13 09:42:08 +08:00
Bowen Wang
218210d26e pci/pci_ivshmem: add pci ivshmem driver support
Add common ivshmem driver, provide the ivshmem bus mechisam, so
many ivshmem based driver can change to pci_ivshmem based

Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
2024-09-10 14:34:31 +08:00
Bowen Wang
ccb17f2bb4 pci/pci_uio_ivshmem: add pci uio ivshmem driver support
Application can open "/dev/uioX" and use `mmap()` to get the
memory provided by ivshmem device.

Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
2024-09-10 14:34:31 +08:00
yangshuyong
75f8c72dbb drivers/pci/pci_qemu_edu: update qemu edu driver code
Signed-off-by: yangshuyong <yangshuyong@xiaomi.com>
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-09-06 10:01:11 +08:00
yangshuyong
9c07b369e9 drivers/pci/pci_qemu_test: update qemu pci test code
Change the qmeu pci test code for new pci driver framework

Signed-off-by: yangshuyong <yangshuyong@xiaomi.com>
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-09-06 10:01:11 +08:00
yangshuyong
125884ae95 Changed the pci bus for arm architecture
Signed-off-by: yangshuyong <yangshuyong@xiaomi.com>
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-09-06 10:01:11 +08:00
Brennan Ashton
69ed5bb67d Various fixes for PCI work
Squashed commits:

1. Porting prior PCI work in place of jailhouse code

At this point the PCI enumeration works for x86_64 including over
pci-pci bridges.

Running QEMU with this configuration we see the bridge and the
device on the bridge.  It also detected the qemu test device

qemu-system-x86_64 \
  -cpu host,+pcid,+x2apic,+tsc-deadline,+xsave,+rdrand \
  --enable-kvm -smp 1 -m 2G -cdrom boot.iso --nographic -no-reboot \
  -device pci-testdev \
  -device pci-bridge,id=bridge0,chassis_nr=2 \
  -device e1000,bus=bridge0,addr=0x3

qemu_pci_init: Initializing PCI Bus
pci_probe_device: [00:00.0] Found 8086:1237, class/revision 06000002
pci_probe_device: [00:01.1] Found 8086:7010, class/revision 01018000
pci_probe_device: [00:01.2] Found ffff:ffff, class/revision ffffffff
pci_probe_device: [00:01.3] Found 8086:7113, class/revision 06800003
pci_probe_device: [00:01.4] Found ffff:ffff, class/revision ffffffff
pci_probe_device: [00:01.5] Found ffff:ffff, class/revision ffffffff
pci_probe_device: [00:01.6] Found ffff:ffff, class/revision ffffffff
pci_probe_device: [00:01.7] Found ffff:ffff, class/revision ffffffff
pci_probe_device: [00:02.0] Found 1234:1111, class/revision 03000002
pci_probe_device: [00:03.0] Found 8086:100e, class/revision 02000003
pci_probe_device: [00:04.0] Found 1b36:0005, class/revision 00ff0000
pci_probe_device: [00:04.0] Probing
pci_check_pci_bridge: [00:05.0] Found Bridge
pci_probe_device: [01:03.0] Found 8086:100e, class/revision 02000003
pci_probe_device: [00:05.0] Found 1b36:0001, class/revision 06040000

2. Remove unused CONFIG_PCI_MAX_BDF option

3. Add a workaround for Jailhouse pci scanning

4. Extend BAR parsing and handle PIO and MMIO for pci-testdev

Signed-off-by: Brennan Ashton <bashton@brennanashton.com>

5. PCI: Add initial support for QEMU 'edu' test device

Signed-off-by: Brennan Ashton <bashton@brennanashton.com>

6. Bring up PCI later in boot process

Signed-off-by: Brennan Ashton <bashton@brennanashton.com>

7. Add ISR and DMA support to QEMU edu test pci device

Signed-off-by: Brennan Ashton <bashton@brennanashton.com>

8. Fix bad function prototype definition in qemu_edu

9. intel64:  Add a pci test configuration and instructions

Signed-off-by: Brennan Ashton <bashton@brennanashton.com>

10. PCI: Fix issue in identification of 64bit bar

Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
2024-01-25 09:09:30 -08:00