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17 Commits

Author SHA1 Message Date
Abdelatif Guettouche
eb403bc996 boards/riscv/esp32c3: Rename the iram_0_2 segment to irom_0_0 to avoid 
confusions.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-24 07:00:51 -05:00
Abdelatif Guettouche
60da4317b9 arch/risc-v/esp32c3: Use the same naming for the RTC heap as ESP32 for 
consistency.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-23 08:37:01 +09:00
Abdelatif Guettouche
f54804bafc arch/risc-v/esp32c3: Create a separate heap for the RTC memory. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-18 00:53:42 -05:00
Abdelatif Guettouche
bd0e03fecf boards/risc-v/esp32c3-devkit/esp32c3.ld: Add the RTC BSS section for 
completeness.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-18 00:53:42 -05:00
Abdelatif Guettouche
61f7bc6e2a boards/risc-v/esp32c3-devkit/scripts: Drop the "iram" in the name of the RTC 
section.

The RTC region is accessed by both I and D buses.  The old name of
`rtc_iram_seg` is a bit confusing.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-18 00:53:42 -05:00
Abdelatif Guettouche
dd4962b2f8 boards/esp32c3-devkit: Add the necessary flags for loadable modules and 
a module defconfig to test the "module" example.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-04 18:08:36 -03:00
Abdelatif Guettouche
3b7ae20843 boards/risc-v/esp32c3-devkit: Add an ELF defconfig and the necessary ELF 
flags and linker script to support that.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-04 18:08:36 -03:00
Dong Heng
76df958e34 riscv/esp32c3: Support SPI Flash encryption read/write 2021-05-23 08:37:25 -03:00
chenwen
16667930cb risc-v/esp32c3: Support ESP32-C3 PM standby and sleep 2021-05-12 10:15:06 -03:00
Dong Heng
fcd5648bca riscv/esp32c3: Fix SPI Flash driver internal chip data address error 
"g_rom_flashchip" is not in fixed address between all ESP32-C3's different versions.
 2021-04-28 09:58:16 -05:00
Gustavo Henrique Nihei
ba23526e39 boards/esp32c3-devkit: Allocate .noinit in a dedicated section 
Previously it was being allocated into .bss section after the _ebss
address. Although functional, this is not intuitive.
 2021-04-28 15:40:49 +01:00
Dong Heng
31854ca135 riscv/esp32c3: Fix heap end address 2021-04-12 01:36:11 -05:00
Alin Jerpelea
3d96d5f2ce arch: esp32: Mixed Case identifier fix 
Fix Mixed Case Identifier reported by nxstyle

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-04-01 12:13:12 -05:00
Alan Carvalho de Assis
4f8ff0765f risc-v/esp32c3: Add SPIFlash support 
Co-Authored-By: Dong Heng <dongheng@espressif.com>
Co-authored-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
Co-authored-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-03-26 09:19:25 +01:00
Dong Heng
458caf2732 riscv/esp32c3: Add ESP32-C3 WLAN netcard driver 2021-03-16 10:42:32 -03:00
Gustavo Henrique Nihei
7fe096c65e risc-v: Fix typos reported by codespell 2021-02-25 16:25:47 +00:00
Abdelatif Guettouche
5562f08369 boards: Add the ESP32-C3 DevKit board 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-02-18 01:21:53 -08:00