Commit Graph

251 Commits

Author SHA1 Message Date
Ville Juven
1b7a95c756 arch/imx9: Add PSCI (system reset) support
ARMv8.2-A has PSCI -> it also has support for system reset
2024-04-23 21:30:56 +08:00
Jukka Laitinen
33d0276f3e arch/arm64/src/imx9/imx9_lpuart.c: Change ARMV8M_DCACHE_LINESIZE -> ARMV8A_DCACHE_LINESIZE
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-04-20 18:43:41 +08:00
Jukka Laitinen
155c776ba8 arch/arm64/src/imx9/imx9_usbdev.c: Fix the descriptor alignments and cache management
Align all the dtd and dqh on cache line boundaries and clean up the cache management

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-04-20 18:43:41 +08:00
Ville Juven
d73aab9f71 arm64/imx9: Add LPSPI driver
Add driver for LPSPI

Co-authored-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-04-18 10:58:02 -03:00
Ville Juven
169dd50a08 imx9_gpioirq: Fix testing of ICR field from pinset
icr is tested below with macros like GPIO_INT_LOWLEVEL et al. Those macros
are shifted left by GPIO_INTCFG_SHIFT, so the temporary icr variable
should not be shifted right.
2024-04-18 00:40:07 +08:00
Ville Juven
09a6c400f6 imx9_boot.c: Add initialization of pin interrupts
Initialize the pin interrupt support during boot
2024-04-18 00:40:07 +08:00
Jukka Laitinen
58f0ee6364 arch/arm64/src/imx9: Add a more capable uart driver
Add an uart driver supporting LPUART1-8, dma, flow control, tc etc.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-04-17 00:10:10 +08:00
Ville Juven
4a82838be7 imx9_iomux.h: Fix issues with the header file
- Add missing include guard
- Add missing C++ guard
- Fix the initialization ordering in IOMUX_PADCFG macro. Why ? Becaused of:

imx9_iomuxc.h:54:3: error: designator order for field 'iomux_padcfg_s::dsyreg' does not match declaration order in 'iomux_padcfg_s'
   54 |   }
      |
2024-04-16 10:56:33 -03:00
Ville Juven
f8c5b91522 arm64/imx9: Add LPI2C driver 2024-04-16 19:14:43 +08:00
Ville Juven
8e32a3ce24 imx93_gpioirq: Fix the GPIO interrupt source names
The original assumption was that the interrupt numbers are divided
so that 16 pins from 1 port are handled by a single interrupt source.

So source 0 would handle pins 0-15 and source 1 would handle pins 16-31.
This assumption is wrong, each pin has two sources, thus there are two
interrupt lines for each pin.

The driver uses source 0, and leaves source 1 disabled.
2024-04-16 19:11:31 +08:00
simbit18
b0504f1e5e fix nxstyle
fix Relative file path does not match actual file.
2024-04-15 15:33:17 -03:00
Ville Juven
2e638f6f19 arch/arm64: Add atomic modifyregXX
These are needed by drivers
2024-04-15 11:53:13 -03:00
Jukka Laitinen
729e9fc8e3 arch/arm64/src/Toolchain.defs: Add -mcpu=cortex-a55 if CONFIG_ARCH_CORTEX_A55 is defined
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-04-09 19:39:33 -03:00
Xiang Xiao
4ea2aeff6b arch: Remove xxx_intstack_top and xxx_intstack_alloc
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2024-04-09 16:59:00 -03:00
ligd
4e725ecd44 arch: color the intstack for all the CPUs
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-04-09 16:59:00 -03:00
ligd
3844efb5b8 stack: update up_get_intstackbase API to support cpu id
For crash dump all the CPU intstack

Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-04-09 16:59:00 -03:00
Jukka Laitinen
5e5640992d arch/arm64/src/imx9/imx9_flexio_pwm.c: Fix wrong input scale and pulse width
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-04-08 03:02:42 +08:00
W-M-R
0ede3fc377 kasan: Implementing global variable out of bounds detection
Extracting global variable information using scripts:
kasan_global.py:
1. Extract the global variable information provided by the -- param asan globals=1 option
2. Generate shadow regions for global variable out of bounds detection
Makefile:
1. Implement multiple links, embed the shadow area into the program, and call it by the Kasan module

Signed-off-by: W-M-R <mike_0528@163.com>
2024-04-07 23:31:13 +08:00
Jukka Laitinen
0f596ec496 arch/arm64/src/imx9: Add TPM based PWM driver for IMX9
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-04-05 10:13:32 -03:00
Jukka Laitinen
62a64b06bc arch/arm64/src/imx9: Add imx9 usb device driver
This is a modified version from imxrt driver, which has the same controller.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-04-04 15:47:32 -03:00
Jukka Laitinen
d1d5a4abfe arch/arm64/src/imx9/hardware/imx93/imx93_memorymap.h: Clean up some base address macros
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-04-04 15:47:32 -03:00
Jukka Laitinen
4d3b753a1a arch/arm64/include/imx9/imx93_irq.h: Define IRQ_USBx interrupt numbers
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-04-04 15:47:32 -03:00
Jukka Laitinen
47f37e84ba arch/arm64/src/imx9: Flex-IO based PWM driver for imx9
This is a high resolution PWM driver, utilizing one 16-bit Flex-IO timer for
generating PWM period and the rest of the timers to generate PWM duty cycles.

This means that the period has to be the same for every PWM generated from one
FLEXIO block, but this way we can get 16-bit resolution for the PWM signals.

For a typical IMX9 HW there are 8 timers for each Flex-IO block, which means
that by using this driver one can get 7 PWM outputs from one block.

This driver can be later extended to have configuration options to use all
8 channels per flex-io by either using 8+8 -bit timer (less resolution) or by
using an external trigger from an LPIT.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-04-04 23:17:59 +08:00
Ville Juven
3294598541 arm64/imx9: Add GPIO, IOMUX and external interrupt support
This adds memory mapped registers and drivers for digital I/O.
2024-04-04 12:12:01 +08:00
Ville Juven
f50c439f21 imx9_clockconfig.c: Add way to query clock frequency
The frequency of a clock source is stored in a LUT. Currently the
LUT contains the PLL frequencies set by the boot ROM code.
2024-04-04 12:12:01 +08:00
Ville Juven
6a6798ed31 arch/arm64: Add the head obj to libarch.a as well
On other platforms libarch.a contains the head object. Some projects
depend on this fact so let's provide the head object in the archive here
as well.
2024-03-25 20:38:53 +08:00
Ville Juven
738bdb95b7 arm64_head.S: Add explicit input section for __start
As __start must be placed at a precise location, a separate, explicit
input section is needed to guarantee this.

Why is this an issue ? NuttX uses --entry=__start which puts __start in
its correct location, but out-of-tree builds won't work, so it more robust
to use an explicit section for the startup code and enforce its placement
in the linker script.
2024-03-23 00:21:54 +08:00
Ville Juven
00986bdd09 arm64/imx9: Add register definitions for LPTMR 2024-03-22 21:37:35 +08:00
Ville Juven
0b8f6af3d6 arm64/imx9: Add register definitions for LPIT 2024-03-22 21:37:35 +08:00
Ville Juven
d2373f4569 arm64/imx9: Add CCM (Clock Controller Module) 2024-03-22 21:37:35 +08:00
Jukka Laitinen
a54f7ffaa8 arch/arm64/src/common: Remove void * arithmetic
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-03-22 09:48:31 +08:00
Ville Juven
46bd210ae4 arm64/imx9: Add support for imx9 series SoMs, imx93 implemented
Adds support for NXP i.MX9-series System-on-Module chips.

- Support for i.MX93 is added
- CPU is Cortex A55 / ARMv8.2A
  - The chip also contains a Cortex M33, but no support is provided
- Supported drivers include lpuart only for now
2024-03-20 20:13:14 +08:00
Ville Juven
8d52020fe1 arm64_internal.h: Expose prototype for arm64_lowputc
Useful procedure in many places.
2024-03-20 20:13:14 +08:00
Ville Juven
2bed7c4646 arm64_mmu: Add data synchronization barrier after page tables are written
The page tables must be committed to system memory before we can proceed
enabling the MMU. ISB() is not enough to do this.
2024-03-19 15:46:51 -03:00
zhangyuan21
9c0d2e1a3c armv7-a/gicv2: move IRQ to group1 and group0 as the FIQ
Purpose: make the the os crash when busyloop with interrupt disable

Follow the arm gicv2 spec, if we want to use the IRQ and FIQ
simultaneously when not using the processor Security Externsions.
We should:
1. IRQ to Group 1 and FIQ to Group 0;
2. Set CICC_CTLR.FIQEn to 1;

Then in NuttX:
1. implement the arm_decodefiq and directly crash in it;
2. provide interface to change the IRQ to FIQ, e.g. change the
   watchdog IRQ to FIQ, so the watchdog can trigger even with the
   interrupt disabled (up_irq_save() called);

Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-03-19 18:24:42 +09:00
Yanfeng Liu
a66c7c3ee1 comments/docs: fix typos in comments
This fix some typos in comments.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-03-06 13:31:50 +08:00
trns1997
54e9e582d5 Use C++ standard lib from toolchain
Signed-off-by: trns1997 <trns1997@gmail.com>
2024-03-06 08:42:44 +08:00
Tiago Medicci Serrano
ae9ef972c0 paging: Rename existing CONFIG_PAGING to CONFIG_LEGACY_PAGING
Current `CONFIG_PAGING` refers to an experimental implementation
to enable embedded MCUs with some limited RAM space to execute
large programs from some non-random access media.

On-demand paging should be implemented for the kernel mode with
address environment implementation enabled.
2024-03-05 09:45:49 +08:00
Marco Casaroli
447cc9698f use apps-or-nuttx-Make.defs for archs
This will allow apps to tweak build configuration of NuttX
2024-03-01 12:59:16 -03:00
ligd
2241969e5a SMP: fix crash when switch to new task which is still running
cpu0 thread0:                        cpu1:
sched_yield()
nxsched_set_priority()
nxsched_running_setpriority()
nxsched_reprioritize_rtr()
nxsched_add_readytorun()
up_cpu_pause()
                                     IRQ enter
                                     arm64_pause_handler()
                                     enter_critical_section() begin
                                     up_cpu_paused() pick thread0
                                     arm64_restorestate() set thread0 tcb->xcp.regs to CURRENT_REGS
up_switch_context()
  thread0 -> thread1
arm64_syscall()
    case SYS_switch_context
     change thread0 tcb->xcp.regs
    restore_critical_section()
                                     enter_critical_section() done
                                     leave_critical_section()
                                     IRQ leave with restore CURRENT_REGS
                                     ERROR !!!

Reason:
As descript above, cpu0 swith task: thread0 -> thread1, and the
syscall() execute slowly, this time cpu1 pick thread0 to run at
up_cpu_paused(). Then cpu0 syscall execute, cpu1 IRQ leave error.

Resolve:
Move arm64_restorestate() after enter_critical_section() done

This is a continued fix with:
https://github.com/apache/nuttx/pull/6833

Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-03-01 21:05:00 +09:00
Yanfeng Liu
3c327efd2f docs/comments: fix some typos
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-01-15 13:22:13 +08:00
chao an
181a31801d arm/armv8r: remove unused serial_pl011.h
Signed-off-by: chao an <anchao@lixiang.com>
2024-01-11 13:39:06 +01:00
fangxinyong
c479ccb8aa sched: move etc romfs mount from nsh to sched/init
Usually the startup script is placed under /etc. The contents of the etc directory
are compiled and linked with Nuttx binary in the form of romfs. After startup,
it will be  mounted by Nsh.

etc is generated by the different boards, that use genromfs and xxd tools to generate
and compile it into the Nuttx, for example: boards/arm/at32/at32f437-mini/tool/mkromfs.sh
The more common method is etc image generated from the content in the corresponding
board/arch/board/board/src/etc directory, and added by Makefile for example:
boards/sim/sim/sim/src/etc.

But in kernel/protected mode, Nuttx kernel and apps are run in different privileged/
non-privileged mode or the isolated binarys, so as that nsh should use syscall to
access Nuttx kernel by exported API. In this scenario, nsh can not mount the etc image
content, because that is generated in board and as a part of Nuttx kernel.

changes:

- move etc romfs mount from nsh to Nuttx, but keep the script to parse and execute.
- move and rename the related CONFIG, move customized nsh_romfsimg.h to etc_romfs.c
  in boards, and no need declaration for romfs_img/romfs_img_len.

This commit changes and updates all configurations in Nuttx arch/board as much as possible,
but if any missing, please refer to the following simple guide:

- rename CONFIG_NSH_ROMFSETC to CONFIG_ETC_ROMFS, and delete CONFIG_NSH_ARCHROMFS in defconfig
- rename the etc romfs mount configs, for example CONFIG_NSH_FATDEVNO to CONFIG_ETC_FATDEVNO
- move customized nsh_romfsimg.h to etc_romfs.c in board/arch/board/board/src and no need
  declaration for romfs_img/romfs_img_len.
- delete default nsh_romfsimg.h, if ROMFSETC is enabled, should generate and compile etc_romfs.c
  in board/arch/board/board/src.

Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
2024-01-09 21:29:46 -03:00
yinshengkai
9d436b624b tools: support sorting symbol tables by name
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2024-01-04 09:22:57 -08:00
xuxin19
524425573e CMake:init arm64 CMake qemu-armv8a build
this patch contains arm64 Toolchain, arch common, qemu board and arm64 libc modifications.
support using CMake to compile the qemu executable file.

```
 cmake -B build -DBOARD_CONFIG=qemu-armv8a:nsh -GNinja
 cmake --build build -t menuconfig
 cmake --build build
 qemu-system-aarch64 -cpu cortex-a53 -nographic -machine virt,virtualization=on,gic-version=3 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx
```
Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2023-12-27 07:27:17 -08:00
yinshengkai
9852428953 fs: procfs add poll support
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2023-12-26 19:23:13 -08:00
Masayuki Ishikawa
40843b79eb arch: arm64: Fix GICv2 detection
Summary:
- I noticed that qemu-armv8a:netnsh_smp_hv does not detect
  GICv2 on Raspi4B (ubuntu 22.04 server + qemu-8.1.2)
- According to the GIC-400 TRM, it says that the architecture
  version can be obtained from GICC_IIDR (See Table 3-7)
- This commit fixes this issue.

Impact:
- Should be none

Testing:
- Tested with qemu-armv8a:netnsh_smp_hv on
  - Raspi3B+ (ubuntu 22.04 server + qemu-8.1.2)
  - Raspi4B (ubuntu 22.04 server + qemu-8.1.2)
  - M1/MacBook Pro 2021 (macOS 13.6 + qemu-8.1.2)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2023-12-21 01:21:20 -08:00
Xiang Xiao
ca5a9c711a Remove @ and % tag from all comments
and format the multiple line comments

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-12-11 17:00:10 -03:00
anjiahao
7dfbd14eba libc: add instrument api support
Add registration function instrumentation API,
which can achieve instrumentation of entering and
exiting functions through the compiler's functionality.

We can use CONFIG_ARCH_INSTRUMENT_ALL to add instrumentation for all
source, or add '-finstrument-functions' to CFLAGS for Part of the
source.

Notice:
1. use CONFIG_ARCH_INSTRUMENT_ALL must mark _start or entry noinstrument_function,
   becuase bss not set.
2. Make sure your callbacks are not instrumented recursively.

use instrument_register to register entry function and exit function.
They will be called by the instrumented function

Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2023-12-11 02:06:51 -08:00
anjiahao
90517b9f11 coredump:support arm64 coredump
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2023-12-08 21:33:03 -03:00