ligd
36a0978952
arch/risc-v/src/rv32im: update & complete risc-v rv32im arch
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1. add schedulesigaction.c
2. add SYS_save_context handling
3. Skip ECALL instruction when up_swint()
Change-Id: Id52c6dd9ee1052441957b73463c00d3fd26555c5
Signed-off-by: ligd <liguiding@fishsemi.com>
2020-06-30 09:31:21 -03:00
Nathan Hartman
679b4fbee2
arch: Fix included directed -> included directly
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This typo had been copied and pasted into numerous irq and syscall
headers.
2020-04-05 22:31:15 +01:00
Xiang Xiao
68951e8d72
Remove exra whitespace from files ( #189 )
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* Remove multiple newlines at the end of files
* Remove the whitespace from the end of lines
2020-01-31 09:24:49 -06:00
Xiang Xiao
6a3c2aded6
Fix wait loop and void cast ( #24 )
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* Simplify EINTR/ECANCEL error handling
1. Add semaphore uninterruptible wait function
2 .Replace semaphore wait loop with a single uninterruptible wait
3. Replace all sem_xxx to nxsem_xxx
* Unify the void cast usage
1. Remove void cast for function because many place ignore the returned value witout cast
2. Replace void cast for variable with UNUSED macro
2020-01-02 10:54:43 -06:00
Ken Pettit
201a32cf8c
Add support for the RISC-V architecture and configs/nr5m100-nexys4 board. I will be making the FPGA code for this available soon (within a week I would say). The board support on this is pretty thin, but it seems like maybe a good idea to get the base RISC-V stuff in since there are people interested in it.
2016-10-16 09:47:07 -06:00
