2 Commits

Author	SHA1	Message	Date
Ville Juven	9b5746cb5f	riscv/barrier: Define more granular memory barriers ... Separate barriers for full (memory + I/O) and local memory (cache) flushing.	2023-06-14 16:14:57 -03:00
Ville Juven	9269a86d00	RISC-V: Add common data memory and instruction barriers	2022-03-18 18:20:12 +08:00