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33 Commits

Author SHA1 Message Date
Gregory Nutt
aae306e942 i.MX6 SMP: Inter-CPU data no saved in a non-cacheable region. 2016-11-26 12:04:02 -06:00
Aleksandr Vyhovanec
472115eda9 ARMv7-M: Add support for the IAR compiler 2016-04-02 08:14:09 -06:00
Gregory Nutt
666cc280f4 Rename irqenable() to up_irq_enable(); rename irqdisable() to up_irq_disable() 2016-02-14 16:54:09 -06:00
Gregory Nutt
83bc1c97c3 Rename irqsave() and irqrestore() to up_irq_save() and up_irq_restore() 2016-02-14 16:11:25 -06:00
Gregory Nutt
36726b1bc4 Standardize the width of all comment boxes in header files 2015-10-02 17:42:29 -06:00
Gregory Nutt
cbdafb96d5 Remove unused function setipsr. Cortex-M IPSR register is not writable 2015-09-23 08:38:32 -06:00
Gregory Nutt
29136e51cc Clean up and review of header files for conformance to standards 2015-06-12 19:26:01 -06:00
Gregory Nutt
f72079cc63 Update COPYING file with special license requirements for PPPD 2015-03-11 09:14:15 -06:00
Gregory Nutt
9bcdf974a0 Add new common lazy FPU state saving option for ARMv7-M. Not yet verified 2015-03-06 08:26:43 -06:00
Gregory Nutt
e11679acf8 Rename CONFIG_NUTTX_KERNEL to CONFIG_BUILD_PROTECTED; Partially integrate new CONFIG_BUILD_KERNEL 2014-08-29 14:47:22 -06:00
Gregory Nutt
8dd679e875 ARMv7-A: Add SYSCALL handling logic 2014-08-28 14:52:14 -06:00
Gregory Nutt
cbf0141d6c Add an ARMv7-A system call definition header file 2014-08-28 13:21:36 -06:00
Gregory Nutt
9e941f1195 Change bne to bne.n in irqrestore() 2014-05-22 09:01:25 -06:00
Gregory Nutt
25d4ff745b More trailing whilespace removal 2014-04-13 16:22:22 -06:00
Gregory Nutt
36ead78f07 ARMv6-M/ARMv7-M: Correct a register handling error in signal delivery (Kernel build mode only). Noted by Mike Smith. 2014-02-23 08:25:49 -06:00
Gregory Nutt
a8004f9e07 Fix major misthink in Cortex-M0 port: The Cortex-M0 has no BASEPRI register. We have to revert to using the nasty PRIMASK register 2013-04-16 18:00:59 -06:00
patacongo
3e7db57403 Rework of kernel build signal dispatch to user-space handlers 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5778 42af7a65-404d-4744-a932-0658087f49c3
 2013-03-23 14:46:02 +00:00
patacongo
4d3d2f2112 A few fixes related to dispatched signals in kernel mode (there are still issues) 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5777 42af7a65-404d-4744-a932-0658087f49c3
 2013-03-22 21:59:05 +00:00
patacongo
87bb6ceb5b Fix syscall parameter passing for the case where the number of parameters is >4 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5767 42af7a65-404d-4744-a932-0658087f49c3
 2013-03-21 00:25:17 +00:00
patacongo
990c1febf8 Add support for nested system calls 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5752 42af7a65-404d-4744-a932-0658087f49c3
 2013-03-17 16:13:28 +00:00
patacongo
c702374d7b Add support for calling to and returning from signal handlers in in user-mode threads 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5750 42af7a65-404d-4744-a932-0658087f49c3
 2013-03-17 00:40:49 +00:00
patacongo
d256021c41 More MPU-related fixes 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5746 42af7a65-404d-4744-a932-0658087f49c3
 2013-03-16 00:34:43 +00:00
patacongo
8159804f9c Fix some ARMv7-M syscall logic 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5736 42af7a65-404d-4744-a932-0658087f49c3
 2013-03-12 21:53:18 +00:00
patacongo
bd1488bdab Fix some bad syscall dispatching log. This change is not testable until these is a tested NuttX kernel build. 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5713 42af7a65-404d-4744-a932-0658087f49c3
 2013-03-06 19:56:32 +00:00
patacongo
30d1159097 More logic to use BASEPRI to control interrupts -- still doesn't work 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5547 42af7a65-404d-4744-a932-0658087f49c3
 2013-01-22 14:37:17 +00:00
patacongo
5ab31d456e Add option to use BASEPRI instead of PRIMASK to disable interrupts in all ARMv7-M architectures 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5546 42af7a65-404d-4744-a932-0658087f49c3
 2013-01-22 01:25:40 +00:00
patacongo
5acf2fe3e1 Resync new repository with old repo r5166 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5154 42af7a65-404d-4744-a932-0658087f49c3
 2012-09-17 18:35:37 +00:00
patacongo
36df84c843 Email address change in nuttx/ 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5145 42af7a65-404d-4744-a932-0658087f49c3
 2012-09-13 18:32:24 +00:00
patacongo
c7aa0b0a23 Incoporate (more) new ARMv7-M exception handling logic contributed by Mike Smith 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4414 42af7a65-404d-4744-a932-0658087f49c3
 2012-02-22 18:44:34 +00:00
patacongo
6e2a5140fb Incoporate new ARMv7-M exception handling logic contributed by Mike Smith 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4413 42af7a65-404d-4744-a932-0658087f49c3
 2012-02-22 18:14:18 +00:00
patacongo
599b52fb69 Add support for the Cortex-M4 floating pointing 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4144 42af7a65-404d-4744-a932-0658087f49c3
 2011-12-07 18:58:21 +00:00
patacongo
2dbde8d001 Add storage space for FPU registers in context switching 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4143 42af7a65-404d-4744-a932-0658087f49c3
 2011-12-07 15:36:46 +00:00
patacongo
f93b962f28 Name change: Change Cortex-M3 naming to ARMv7-M naming so support Cortex-M4 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3846 42af7a65-404d-4744-a932-0658087f49c3
 2011-08-05 21:57:49 +00:00