Gregory Nutt
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e59924a9e6
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SAMA5 EHCI: Fix some list traversal bugs
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2013-08-22 19:32:24 -06:00 |
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Gregory Nutt
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b7330bc849
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SAMA5 EHCI: Initial debug changes
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2013-08-22 17:25:00 -06:00 |
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Gregory Nutt
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e581bfeb29
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SAMA5 EHCI: No complete for bulk and control endpoints
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2013-08-22 13:36:16 -06:00 |
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Gregory Nutt
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ea2e4c11f8
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SAMA5 EHCI: Add data transfer logic for asynchronous endpoints
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2013-08-22 10:27:46 -06:00 |
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Gregory Nutt
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da3ff83fc3
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SAMA5 EHCI: Add IOC error handling
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2013-08-22 09:23:01 -06:00 |
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Gregory Nutt
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73efdf8d05
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SAMA5 EHCI: transfer termination logic. Incomplete
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2013-08-21 17:08:12 -06:00 |
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Gregory Nutt
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f831c8fe94
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SAMA5 EHCI: Hardware initialization logic
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2013-08-21 13:45:54 -06:00 |
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Gregory Nutt
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c109c39be7
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Move all SAMA5 EHCI interrupt handling to the worker thread
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2013-08-21 11:07:42 -06:00 |
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Gregory Nutt
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9f6ae9332f
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SAMA5 EHCI: At list-oriented cache operations
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2013-08-20 18:06:04 -06:00 |
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Gregory Nutt
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514826eeb1
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Add SAMA5 EHCI list traversal logic
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2013-08-20 17:01:30 -06:00 |
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Gregory Nutt
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6a79cea2c0
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Beginning of support for SAMA5 EHCI. Not much there yet
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2013-08-20 15:46:36 -06:00 |
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Gregory Nutt
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609dc65235
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Add kernel/user memalign functions. Not fully integrated
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2013-08-20 13:04:49 -06:00 |
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Gregory Nutt
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4d5789dfdd
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SAMA5 OHCI+EHCI mostly cosmetic changes
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2013-08-19 15:03:14 -06:00 |
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Gregory Nutt
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4bf3dbe149
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USB host: Add device address management support in preparation for USB hub support
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2013-08-18 14:31:57 -06:00 |
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Gregory Nutt
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a6e6b4ba2d
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Add few more EHCI definitions
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2013-08-18 13:01:13 -06:00 |
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Gregory Nutt
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07bd7c2168
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STM32 F1 I2C: Fix a typo that crept in with some recent changes. From Yiran Liao
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2013-08-18 07:45:14 -06:00 |
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Gregory Nutt
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b33de2b618
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Add EHCI header file (not quite complete)
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2013-08-17 14:19:18 -06:00 |
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Gregory Nutt
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a0837fca6c
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SAMA5 OHCI: Driver is now basically functional
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2013-08-16 13:13:21 -06:00 |
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Gregory Nutt
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db42d9350c
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SAMA5 OHCI: Re-organize some endpoint list data structures.. Strange things happen when semaphores lie in DMA memory which is occasionally invalidated
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2013-08-16 11:36:51 -06:00 |
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Gregory Nutt
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ddc93e1da3
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STM32 SPI: nbits interface extended to handle LSB- or MSB-first operation. From Teemu Pirinen
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2013-08-16 11:35:22 -06:00 |
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Gregory Nutt
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94bcdc66b0
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SAMA5 OHCI: Don't prealloc RH port TDs and EDs. Allocate from a free list like other cases
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2013-08-15 17:15:08 -06:00 |
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Gregory Nutt
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41c068f652
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SAMA5 OHCI: Fix errors in cache handling; Don't add ED to control list until port is connected
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2013-08-15 15:28:27 -06:00 |
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Gregory Nutt
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e23a92243c
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SAMA5: ports should not be reset state (seems to make no difference)
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2013-08-14 17:33:31 -06:00 |
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Gregory Nutt
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49f3831e11
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SAMA5: Alternatie clock configuration that yields a perfect 48MHz full speed USB clock and a CPU clock of 384MHz
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2013-08-14 15:16:04 -06:00 |
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Gregory Nutt
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e32b60a78c
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SAMA5 OHCI: Use physical address and flush and/or invalidate data caches as necessary
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2013-08-14 12:23:06 -06:00 |
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Gregory Nutt
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bdbe4a4f25
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Clean up some LP17xx and STM32 USB host configuration compilation errors due to the massive changes to the USB host interfaces needed to support the SAMA5
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2013-08-13 17:43:19 -06:00 |
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Gregory Nutt
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8f429fd54d
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SAMA5: Major restructuring of the the OHCI driver drivers to better handle the multiple root hub ports and concureent transfers on each port.
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2013-08-13 16:48:14 -06:00 |
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Gregory Nutt
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34418d12bb
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Separate wait() and enumerate() methods from struct usbhost_driver_s and move to new interface, struct usbhost_connection_s. This is part of the necessary restructuring of the USB host interface to support multiple root hub ports.
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2013-08-13 15:03:46 -06:00 |
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Gregory Nutt
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b4645f73ec
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Back out most of the changes of 3b04d08043742b9e65cf38d45988b35bff91daed
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2013-08-13 14:12:27 -06:00 |
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Gregory Nutt
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d0fbea35eb
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Separate SAMA5 OHCI interrupt handling into separate functions
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2013-08-13 13:34:35 -06:00 |
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Gregory Nutt
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7339c1c5e6
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SAMA5 OHCI: Fix some erors in the loop that waits for device connection changes
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2013-08-13 09:44:16 -06:00 |
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Gregory Nutt
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6d72cccdf0
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Fix re-entry problem in SAMA5 up_putc
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2013-08-13 09:42:40 -06:00 |
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Gregory Nutt
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f3bfd6a515
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STM32 F3 fixes from John Wharington
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2013-08-13 07:48:18 -06:00 |
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Gregory Nutt
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a4c195482f
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More changes to USB host interface to support multiple downstream ports
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2013-08-12 16:29:33 -06:00 |
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Gregory Nutt
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39696cbf96
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First of several changes needed to support multiple USB host root hubs
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2013-08-12 14:44:06 -06:00 |
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Gregory Nutt
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f5a0ce709c
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SAMA5: Add logic to control VBUS power for OHCI
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2013-08-12 11:59:10 -06:00 |
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Gregory Nutt
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dfe6452b8e
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Add untested OHCI driver for the SAMA5; structure naming and header files for USB host initialization prototypes
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2013-08-11 17:11:32 -06:00 |
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Gregory Nutt
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9cf1365cde
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SAMA5: Some improvements to the HSCMI card removal/insertion logic
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2013-08-11 11:13:11 -06:00 |
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Gregory Nutt
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69bc6afbd3
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Add CAN configuration to STM32 config menu
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2013-08-10 19:37:35 -06:00 |
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Gregory Nutt
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03130ca5a3
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STM32: Fix STM32 serial init for non-reordered serial ports. From Lorenz Meier
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2013-08-10 19:33:16 -06:00 |
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Gregory Nutt
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217ed87aad
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Added option to disable STM32 serial port re-ordering
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2013-08-10 19:29:44 -06:00 |
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Gregory Nutt
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3c38992727
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SAMA5: Fix HSMCI race condition. Now memory card interface is functional with DMA
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2013-08-10 18:01:23 -06:00 |
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Gregory Nutt
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6622714c5d
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Rearrange configuration settings so that ARCH_HAVE_SDIO is moved to higher, sharable level
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2013-08-10 09:06:53 -06:00 |
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Gregory Nutt
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75d0fc2a10
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Extend the virtual-to-physical address conversion logic to handle NFS SRM, UDPH SRAM, and external SRAM and PSRAM.
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2013-08-09 17:55:27 -06:00 |
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Gregory Nutt
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d8b3921972
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SAMA5: Centralize logic for conversion between physical and virtual addresses
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2013-08-09 17:25:53 -06:00 |
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Gregory Nutt
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ad6b8726c2
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Fix some cache-related issues with the SAMA5 DMA driver
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2013-08-09 15:25:13 -06:00 |
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Gregory Nutt
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a2ba8992a9
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SAM3,4,A5 DMA fixes; SAMA5 SPI driver now supports DMA transfers
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2013-08-09 13:12:16 -06:00 |
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Gregory Nutt
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2b36e7e266
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SAMA5: Use RDR/TDR registers for DMA, not FIFO registers; change DMA bit settings to match Atmel example. Still no DMA
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2013-08-08 15:51:16 -06:00 |
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Gregory Nutt
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53c4a1e647
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SAMA5 DMA: Need to flush caches; DMA channel depends upon direction of DMA; the maximum transfer size in bytes depends on the number of bytes per transfer
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2013-08-08 13:15:52 -06:00 |
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Gregory Nutt
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05242e41ef
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More SAMA5 DMAC driver fixes. Still does not work.
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2013-08-07 17:19:48 -06:00 |
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