3 Commits

Author	SHA1	Message	Date
chenrun1	c61195bcc9	arch/armv7-a & armv7-r:Add invalidate icache behavior ... Signed-off-by: chenrun1 <chenrun1@xiaomi.com>	2023-01-16 16:14:32 +08:00
ligd	059497d1d1	armv7-a/r: NON-primary core should invalidate dacache level1 ... NON-primary cpu will invalidate cpu0's cache L2, that will caused cpu0's data mismatch, and then system crash Signed-off-by: ligd <liguiding1@xiaomi.com>	2022-09-27 14:41:39 +08:00
ligd	6d92810d5a	armv7a/r: refact cp15_cache functions ... Signed-off-by: ligd <liguiding1@xiaomi.com>	2022-09-21 18:07:03 +08:00