Previous adjtime() implementation was limited to adjusting system
timer tick period. This commit reimplements the internals to use
a kernel watchdog timer. Platform-independent part of the code now
works also for adjusting hires RTC and tickless timer rate.
User code facing API is unchanged. Architecture code API has changed:
up_adj_timer_period() is replaced by up_adjtime().
Other improvements:
- Support query of remaining adjustment by passing NULL to first
argument of adjtime(). This matches Linux behavior.
- Improve resolution available for architecture driver, previously
limited to 1 microsecond per tick. Now 1 nanosecond per second.
In order to achieve better scalability, change the stride
from pixel mode to byte mode.For example, in the case of RGB888
mode with 466 pixels in width and a 4-byte aligned buffer,it is
only necessary to extend the buffer of one line from 1398 bytes
to 1400 bytes, instead of extending it to 1404 bytes.
Signed-off-by: rongyichang <rongyichang@xiaomi.com>
These values are board-specific properties that must be known on the application side.
Until now, these values had to be hardcoded on the application side.
Summary:
- Upgraded to xpack-riscv-none-elf-gcc-12.3.0-2 to resolve symbol recognition
issues in riscv-none-elf-gdb, as reported in
https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/issues/22.
Impact:
- Expected to enhance toolchain stability with no negative side effects.
Testing:
- Verified with rv-virt:netnsh and rv-virt:netnsh64 configurations
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
When we record data and dump data, they are all executed within the system,
and there is no need to consider the issue of big or small endianness.
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
1. If CONFIG_ESP32S3_PHY_INIT_DATA_IN_PARTITION and CONFIG_ESP32S3_SUPPORT_MULTIPLE_PHY_INIT_DATA are enabled,
PHY initialization data (PHY initialization data is used for RF calibration) will be loaded from a partition.
2. The corresponding PHY init data type can be automatically switched according to the country code,
China's PHY init data bin is used by default, country code can be modified through the wapi command: wapi country <ifname> <country code>.
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
If using flow control with a high CTS the thread may be
blocked forever on the second transmit attempt due to waiting
on the txdma semaphore. The calling thread can then never
make progress and release any resources it has taken, thus
may cause a deadlock in other parts of the system.
The implementation differs in behavior from interrupt-driven
TX. It should not implicitly wait on a taken semaphore but
return immediately and let the upper layers decide on what to
do next.
If using flow control with a high CTS the thread may be
blocked forever on the second transmit attempt due to waiting
on the txdma semaphore. The calling thread can then never
make progress and release any resources it has taken, thus
may cause a deadlock in other parts of the system.
The implementation differs in behavior from interrupt-driven
TX. It should not implicitly wait on a taken semaphore but
return immediately and let the upper layers decide on what to
do next.
If using flow control with a high CTS the thread may be
blocked forever on the second transmit attempt due to waiting
on the txdma semaphore. The calling thread can then never
make progress and release any resources it has taken, thus
may cause a deadlock in other parts of the system.
The implementation differs in behavior from interrupt-driven
TX. It should not implicitly wait on a taken semaphore but
return immediately and let the upper layers decide on what to
do next.
This commit sets the BLE's interrupt as a IRAM-enabled interrupt,
which enables it to run during a SPI flash operation. This enables
us to create a cache to off-load semaphores and message queues
operations and treat them when the SPI flash operation is finished.
By doing that, we avoid packet losses during a SPI flash operation.
This commit provides an interface to register ISRs that run from
IRAM and keeps track of the non-IRAM interrupts. It enables, for
instance, to avoid disabling all the interrupts during a SPI flash
operation: IRAM-enabled ISRs are, then, able to run during these
operations.
It also makes the code look more similar to the ESP32-S3 SPI flash
implementation by creating a common `esp32_spiflash_init` that is
responsible to create the SPI flash operation tasks. The function
intended to initialize the SPI flash partions was, then, renamed to
`board_spiflash_init`.
Whenever we enter/leave a critical section, the interrupt status is
saved and, then, restored. However, for the ESP32's BLE adapter,
entering/leaving a critical section is done on separate functions
that need to be registered as a callback.
The status flag was being saved as a global variable. However,
calling nested enter_critical_section would overwrite this global
variable that was storing the previous flag and, when leaving the
last critical section, the restored status would be different from
the one expected. The proposed solution for this issue is to create
a global array to store the interrupt status flags for nested calls.
During PSRAM initialization and flash operations, the Cache needs to be disabled.
So all data and code for the aforementioned scope is required to be placed in Internal RAM.
