Commit Graph

11 Commits

Author SHA1 Message Date
Stuart Ianna
50f0fd4df2 risc-v/litex: Add system reset and access to core control registers. 2023-08-25 17:16:28 +08:00
Stuart Ianna
4cae98674d litex: Support for kernel build with vexriscv-smp. 2023-04-22 01:40:32 +08:00
Stuart Ianna
05c6d7c7b9 litex: Add PWM driver.
PWM driver for multiple peripherals supplied in gateware.

Only single channel frequency and duty cycle control is implemented. Pulse counting and multichannel features are not currently feasible.

Additions also include a new board configuration for arty-a7 which enables the PWM driver and example application.
2023-02-01 09:34:57 -03:00
Xiang Xiao
7a0fd8d10f arch/risc-v: Remove FAR from chip and board folder
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-19 00:22:45 +03:00
Richard Tucker
3939575d7c boards/risc-v/litex/arty_a7: add SDCARD support for the Arty_A7 board 2022-03-30 02:35:27 +08:00
Xiang Xiao
b12f588140 Rename CONFIG_LIB_BOARDCTL to CONFIG_BOARDCTL
since boardctl isn't a libc feature

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-08-06 13:58:26 +02:00
Xiang Xiao
d7f96003cf Don't include debug.h from public header file
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-06-01 06:42:02 +09:00
Xiang Xiao
9473434587 Ensure the kernel component don't call userspace API
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-03-01 09:23:09 +09:00
Xiang Xiao
1a95cce1a3 build: Move .config check to the top Makefile
remove the workaround to handle the inexistence of .config/Make.defs

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-05-20 17:57:34 +01:00
Nathan Hartman
8d985819b3 Fix typos
Comments only. No functional changes.
2020-05-14 10:49:44 -06:00
aenrbes
d450f5ce77
Add support for Litex VexRiscV. 2020-03-21 06:01:56 +00:00