Commit Graph

46155 Commits

Author SHA1 Message Date
Xiang Xiao
61dff1c125 arch/arm64: Implement up_nputs
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-07-17 17:31:19 +03:00
Xiang Xiao
aad5fbd2fb arch: Add up_nputs function to handle the non '\0' string correctly
and change up_puts as a simple macro

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-07-17 17:31:19 +03:00
Xiang Xiao
02ea79365a drivers/bch: Adjust f_pos with the correct value
Fix the problem reported by:
https://github.com/apache/incubator-nuttx/issues/6619

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-07-17 17:13:36 +03:00
Xiang Xiao
3276438984 procfs/mount: Unify uint[32|64]_t to fsblkcnt_t for the code simplification
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-07-16 21:06:53 +03:00
Xiang Xiao
c211954a42 partition/gpt: Replace PRI?LBA with PRI?OFF
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-07-16 21:04:58 +03:00
Michal Lenc
4484d04a8d samv7: add RX DMA support to serial driver
This commit adds RX DMA support to serial driver. The DMA is currently
supported only for USART peripherals, not for UART. It uses two circular
buffers which size can be setup by SAMV7_SERIAL_RXDMA_BUFFER option.

The idle bus interrupt is enabled to ensures data are read even if the
buffer is not yet full. The timeout can be setup by
SAMV7_SERIAL_DMA_TIMEOUT option.

This adds support only for RX transfers.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2022-07-16 15:39:20 +03:00
Michal Lenc
e3e282bd8a samv7: add DMA API for circular buffers
This commit adds functions sam_dmarxsetup_circular() and
sam_dmarxstart_circular() that create API for operating with two or more
circular buffers. This can be used for DMA operation with serial driver
or ADC where ping pong buffers are required to successfully transfer the
data at high speed.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2022-07-16 15:39:20 +03:00
Michal Lenc
89a2b51b96 samv7: add RS-485 mode support to USART driver
This commit enhances SAMV7 serial driver with RS-485 mode available to
USART peripherals. The hardware automatically sets RTS pin high when
data are transfered and low then no transfer occurs. Only USART peripherals
support this mode, UART peripherals do not.

This mode can be enabled by configuration option SAMV7_USARTx_RS485MODE.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2022-07-16 15:39:20 +03:00
Xiang Xiao
a2239891e7 mmcsd: Remove the not really used capacity field
to avoid the check of CONFIG_HAVE_LONG_LONG in many place

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-07-16 11:12:30 +03:00
raiden00pl
8e5e6ab8cb stm32/Kconfig: stm32_i2s needs SPI_DMA enabled 2022-07-16 11:10:01 +03:00
raiden00pl
1ca8bf2cdb boards: remove references to STM32xx_SPI_DMA, which is now a hidden option 2022-07-16 11:10:01 +03:00
raiden00pl
a8e7f7742c stm32f0l0g0/Kconfig: set default n for hidden options 2022-07-16 11:10:01 +03:00
raiden00pl
d307e5a7f5 stm32f0l0g0/Kconfig: hide STM32F0L0G0_SPI_DMA option and select it automatically 2022-07-16 11:10:01 +03:00
raiden00pl
1b45982521 stm32f0l0g0/Kconfig: remove the duplicated SPI DMA section 2022-07-16 11:10:01 +03:00
raiden00pl
e39afbf277 stm32/Kconfig: set default n for hidden options 2022-07-16 11:10:01 +03:00
raiden00pl
12273d0aa9 stm32/Kconfig: hide STM32_SPI_DMA option and select it automatically 2022-07-16 11:10:01 +03:00
raiden00pl
1616edbb81 stm32f7/Kconfig: hide STM32F7_SPI_DMA option and select it automatically 2022-07-16 11:10:01 +03:00
raiden00pl
6aef19617b stm32h7/Kconfig: hide STM32H7_SPI_DMA option and select it automatically 2022-07-16 11:10:01 +03:00
raiden00pl
cb94579ab7 stm32wl5/Kconfig: hide STM32WL5_SPI_DMA option and select it automatically 2022-07-16 11:10:01 +03:00
raiden00pl
3c0a3dabfc stm32f0l0g0/SPI: add support for half duplex, simplex rx and simplex tx modes 2022-07-16 02:00:53 +08:00
curuvar
d69d9eb0c9 Added I2C Slave to RP2040
Added length to I2C slave callback.
2022-07-16 01:56:52 +08:00
raiden00pl
2428438037 stm32f0l0g0/SPI: fix compilation for DMA enabled 2022-07-15 11:38:36 -03:00
raiden00pl
c7e6366e91 stm32f0l0g0/SPI: enable SPI for STM32G0 2022-07-15 11:38:36 -03:00
raiden00pl
f702c89c33 stm32f0l0g0/SPI: configure DMA support individually for each SPI 2022-07-15 11:38:36 -03:00
raiden00pl
056e11a3e5 stm32f0l0g0/SPI: only SPI1 and SPI2 are present in STM32 M0 devices 2022-07-15 11:38:36 -03:00
raiden00pl
47e29d9402 stm32f0l0g0: remove references to non-existent ADCs, only ADC1 present on STM32 M0/M0+ devices 2022-07-15 11:36:43 -03:00
raiden00pl
9276e41321 b-l072z-lrwan1: use board common logic for ssd1306 2022-07-15 10:22:58 -03:00
raiden00pl
072b2bca45 boards/stm32f0l0g0: add ssd1306 to board common logic 2022-07-15 10:22:58 -03:00
raiden00pl
703e5e4226 boards/stm32f0l0g0: common board logic support 2022-07-15 10:22:58 -03:00
Masayuki Ishikawa
82cd9b0a4a arch: arm64: Add stack coloration for SMP
Summary:
- This commit adds stack coloration for SMP

Impact:
- None

Testing:
- Tested with qemu-a53:nsh_smp

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-07-15 16:16:02 +08:00
Masayuki Ishikawa
3682bcd4b3 arch: arm64: Fix do_stackcheck()
Summary:
- Since the stack coloration is done for every 32bits
  this function should be done in the same way.

Impact:
- None

Testing:
- Tested with qemu-a53:nsh

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-07-15 16:16:02 +08:00
Masayuki Ishikawa
d96c87f666 syscall: Add socketpair to syscall.csv
Summary:
- This commit adds socketpair to syscall.csv

Impact:
- None

Testing:
- Tested with adb (not merged net)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-07-15 13:31:58 +08:00
larry
8f72799e8e net: Fix frame count check fail
bc_rxtail/rxtail should always point to newly frame.
If input more than one frame before receive,
missing assignment can result in old frame lost.

Signed-off-by: larry <larry@transtekcorp.com>
2022-07-14 22:56:05 +03:00
qinwei1
e77b06721b arch: arm64: ARMv8-A support for NuttX
N/A

Summary:

Arm64 support for NuttX, Features supported:

1. Cortex-a53 single core and SMP support: it's can run into nsh shell at
   qemu virt machine.

2. qemu-a53 board configuration support: it's only for evaluate propose

3. FPU support for armv8-a: FPU context switching at NEON/floating-point
  TRAP is supported.

4. psci interface, armv8 cache operation(data cache) and smccc support.

5. fix mass code style issue, thank for @xiaoxiang781216, @hartmannathan @pkarashchenko

Please refer to boards/arm64/qemu/qemu-a53/README.txt for detail

Note:
1. GCC MACOS issue
The GCC 11.2 toolchain for MACOS may get crash while compiling
float operation function, the following link describe the issue
and give analyse at the issue:

https://bugs.linaro.org/show_bug.cgi?id=5825

it's seem GCC give a wrong instruction at certain machine which
without architecture features

the new toolchain is not available still, so just disable the MACOS
cibuild check at present

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2022-07-14 09:35:49 -04:00
xiangdong6
8dbceb77f7 include: Declare nxtask_delete function.
Add nxtask_delete declaration in order to prevent build warnings.

Signed-off-by: xiangdong6 <xiangdong6@xiaomi.com>
2022-07-14 10:44:26 +03:00
Gustavo Henrique Nihei
feca57ffa9 esp32-devkitc: Add knsh configuration to the Documentation page
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-07-14 14:57:57 +08:00
Gustavo Henrique Nihei
68c722c051 xtensa/esp32: Build patched IDFBoot for Protected Mode support
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-07-14 14:57:57 +08:00
Gustavo Henrique Nihei
60b7479f12 xtensa/esp32: Avoid ROM functions due to error with PIDs 2-7
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-07-14 14:57:57 +08:00
Gustavo Henrique Nihei
27fc3c959d xtensa/esp32: Configure the PID controller for privilege separation
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-07-14 14:57:57 +08:00
Gustavo Henrique Nihei
76acfef5ec xtensa/esp32: Add support for Protected Mode
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-07-14 14:57:57 +08:00
Gustavo Henrique Nihei
6f0334140f sched: Convert DEBUGASSERT(false) into more intuitive DEBUGPANIC()
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-07-14 12:08:45 +08:00
Gustavo Henrique Nihei
9b0e3ae9d2 libs: Convert DEBUGASSERT(false) into more intuitive DEBUGPANIC()
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-07-14 12:08:45 +08:00
Gustavo Henrique Nihei
83442aa70c boards: Convert DEBUGASSERT(false) into more intuitive DEBUGPANIC()
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-07-14 12:08:45 +08:00
Gustavo Henrique Nihei
939b990a9c wireless: Convert DEBUGASSERT(false) into more intuitive DEBUGPANIC()
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-07-14 12:08:45 +08:00
Gustavo Henrique Nihei
3948736c41 net: Convert DEBUGASSERT(false) into more intuitive DEBUGPANIC()
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-07-14 12:08:45 +08:00
Gustavo Henrique Nihei
ea0f60cc24 mm: Convert DEBUGASSERT(false) into more intuitive DEBUGPANIC()
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-07-14 12:08:45 +08:00
Gustavo Henrique Nihei
e999708b31 drivers: Convert DEBUGASSERT(false) into more intuitive DEBUGPANIC()
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-07-14 12:08:45 +08:00
Gustavo Henrique Nihei
e24621d545 arch: Convert DEBUGASSERT(false) into more intuitive DEBUGPANIC()
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-07-14 12:08:45 +08:00
Gustavo Henrique Nihei
9695659620 boards: Fix typo in "register" word
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-07-13 22:57:19 +03:00
Gustavo Henrique Nihei
8a4c9c3489 arch: Fix typo in "register" word
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-07-13 22:57:19 +03:00