Alin Jerpelea
29529e8758
arch: mips: nxstyle fixes
...
Nxstyle fixed to pass CI
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-03-31 08:48:33 -07:00
Alin Jerpelea
f3f10a3b96
arch: mips: Author Gregory Nutt: update licenses to Apache
...
Gregory Nutt has submitted the SGA and we can migrate the licenses
to Apache.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-03-31 08:48:33 -07:00
Xiang Xiao
cde88cabcc
Run codespell -w with the latest dictonary again
...
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-02-23 22:27:46 +01:00
Ouss4
0dc1dc605d
arch/mips: When a CPU implements an External Interrupt Controller,
...
use the IPL bits to control masking interrupts.
2020-02-10 12:40:41 -06:00
Gregory Nutt
b21c12bd18
Fix errors found in build testing:
...
arch/mips/src: Previous commit used CP0 register definitions that were not defined in the cp0.h header file. Probably these were from the Microchip hacked up GCC toolchain but are not generally available. Fix: Add definitions to NuttX cp0.h header file.
mm/iob: Eliminate some warnings about testing the value of an undefined pre-processor variable.
2019-05-25 11:45:22 -06:00
Ouss4
3a594d5a1f
arch/mips/src/pic32mz/pic32mz-head.S: Initialize the global pointer in all shadow sets.
2018-10-16 12:25:37 -06:00
Gregory Nutt
ae15c6963c
Make some file section headers more consistent with standard
2015-04-08 08:04:12 -06:00
Gregory Nutt
a4d514c79b
PIC32MX/Z: Partial review of PIC32MZ cp0 register -- need to do more; Also found issues with definitions for PIC32MX -- need to be retested
2015-02-25 13:33:09 -06:00
Gregory Nutt
024a5cb278
PIC32MZ: Add just enough PIC32MZ logic that we can run 'make menuconfig'
2015-02-22 10:53:24 -06:00
