Commit Graph

22163 Commits

Author SHA1 Message Date
Tiago Medicci
c99c3ceec2 up_copy_section: Improve function description
Add "Input Parameters" section to already existing definitions
and declarations of `up_copy_section` function.
2024-07-31 02:33:12 +08:00
Tiago Medicci Serrano
016bc47a63 esp32s3/elf: Enable ELF loader for ESP32-S3
Provide `up_copy_section` function that enables copying data using
the data bus. If the memory destination address is accessible
through the instruction bus, the data is copied using the
correspondent address accessible through the data bus.
2024-07-31 02:33:12 +08:00
zouboan
d74a612a6e zynq-mpsoc/zcu111: independent JTAG configs from normal nsh configs 2024-07-30 12:41:30 -03:00
p-szafonimateusz
07c1f5db92 arch/intel64/irq.h: rename rdtsc macros
rename _rdtsc macro to rdtsc to avoid conflict with external code
rename rdtsc macro to rdtscp to be the same as asm instruction used

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-07-30 21:53:08 +08:00
p-szafonimateusz
90e47bf1f5 arch/x86_64/src/intel64/intel64_cpu.c: remove workaround for spin_lock
remove workaround for spin_lock which is no longer needed after inline splinlock change
2024-07-30 21:40:53 +08:00
adriendesp
cd4fdf27c5 arch/xmc4 : i2c driver
Added lower half i2c driver
2024-07-30 18:23:19 +08:00
Yanfeng Liu
a6c7e68b5d riscv/qemu-rv: skip reloading mhartid
As a0 already has mhartid passed by SBI  or ZSBL, no need to load it
again here.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-07-30 18:20:22 +08:00
Tiago Medicci Serrano
c91599d34c esp32s3/i2s: Fix faulty initialization when SMP is enabled
The buffer initialization function (`i2s_buf_initialize`) calls
`i2s_buf_free`, which performs buffer initialization within a
critical section (`spin_lock_irqsave`). If this function is called
under the same critical section (same spinlock), initialization
will hang.
2024-07-30 01:44:57 +08:00
Tiago Medicci Serrano
1ab1a905b8 esp32s3/i2s: Add CONFIG_ESP32S3_I2S_MAXINFLIGHT to Kconfig
Enable setting the number of in-flight buffers to be used by the
I2S peripheral on ESP32-S3 using Kconfig.
2024-07-30 01:44:57 +08:00
anjiahao
bc1083ac33 arm_backtrace_unwind:Make the backtrace search the entire stack as much as possible
also fixbacktrace crash when idle thread lr is random

Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2024-07-29 22:19:56 +08:00
Eren Terzioglu
98f5d6adc5 esp32[s2|s3]: Add temperature sensor support 2024-07-27 14:12:44 -03:00
Eren Terzioglu
e467a16abe esp32[c3|c6|h2]: Add temperature sensor support 2024-07-27 14:12:44 -03:00
Henry Rovner
23bc78a5b7 bl808_wdt: Expand function headers 2024-07-27 22:59:23 +08:00
Henry Rovner
42eafcdfa5 risc-v/bl808: Add watchdog driver
This change implements a driver for the two watchdog timers on the BL808, and enables it as part of the timer config. The driver is based on the GP timer driver.
2024-07-27 22:59:23 +08:00
Filipe Cavalcanti
91dfd20eaf arch/xtensa: add support for brushed DC motor control
arch/xtensa: add support for capture driver on ESP32 and ESP32|S3|

Squashed:
Initial settings for MCPWM Capture on board level
Created lower half files - compilation ok
Using capture debug features. Simple example on fops works
Successful duty and freq calculation
Documentation update
Fixed and added interupt capabilities for all 3 capture channels
Cleaned defconfig
Renamed macros, added S3 options and moved arch source to common dir
Added support for ESP32S3
Added capture example to defconfig and renamed

Basic bring up ready. New Kconfig options for motor.

Good motor registration

Working on enabling pwm generators

Working on enabling pwm generators

Added fops functions

Success on PWM 50%

stable pwm operation for bdc

Added loopback option for testing

Improved rules on fsm

Working motor direction control

Testing new ISR for fault handling

Issues on fault ISR

Removed fault implementation (not working)

Added support for esp32s3

Documentation improvements

Added default motor spin direction

Added parameter change while running

Review fixes

arch/xtensa: add support for fault signal on motor control

Squashed:
Initial settings for MCPWM Capture on board level
Created lower half files - compilation ok
Using capture debug features. Simple example on fops works
Successful duty and freq calculation
Documentation update
Fixed and added interupt capabilities for all 3 capture channels
Cleaned defconfig
Renamed macros, added S3 options and moved arch source to common dir
Added support for ESP32S3
Added capture example to defconfig and renamed

Basic bring up ready. New Kconfig options for motor.

Good motor registration

Working on enabling pwm generators

Working on enabling pwm generators

Added fops functions

Success on PWM 50%

stable pwm operation for bdc

Added loopback option for testing

Improved rules on fsm

Working motor direction control

Testing new ISR for fault handling

Issues on fault ISR

Removed fault implementation (not working)

Added support for esp32s3

Documentation improvements

Added default motor spin direction

Added parameter change while running

Got responsive fault indicator

Working brakes - still need to work on starting isr

Fixed single-time ISR initializiation

Working soft brake on fault

Improved KConfig for BDC and BLDC

Kconfig fixed at board level
2024-07-27 12:08:51 +08:00
Huang Qi
d7f82fb14c Correct comment blocks
Fix wrong comment blocks in the following files:
- arch/arm/src/stm32f0l0g0/stm32_pwr.c
- include/nuttx/mtd/nand_config.h

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-07-27 03:11:39 +08:00
Huang Qi
3b70bf7ff0 samv7: Fix comment block in sam_rstc.h
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-07-27 03:11:39 +08:00
raiden00pl
e75c19ce58 arch/arm/{nrf53|nrf91}: enable fpu if CONFIG_ARCH_FPU=y
enable fpu if CONFIG_ARCH_FPU=y, the previous condition depended on CONFIG_ARCH_HAVE_FPU=y
2024-07-26 23:46:34 +08:00
buxiasen
f5021021ae up_backtrace: fix maybe backtrace the exiting thread
when the thread to backtrace is exiting, get_tcb and up_backtrace in
different critical section may cause try to dump invalid pointer, have
to ensure the nxsched_get_tcb and up_backtrace inside same critical
section procedure.

Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2024-07-26 12:03:43 +08:00
Yanfeng Liu
9e59b0b43b riscv/qemu: guard u16550 uses
This guards the uses for u16550 serial initialization, just in case
that no u16550 is configured.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-07-26 12:01:29 +08:00
Henry Rovner
049a6da098 risc-v/bl808: Add timer driver
This change implements a driver for the hardware timer blocks on the BL808, as well as a config with the timer example enabled.
2024-07-24 10:06:54 +08:00
nuttxs
a83a569652 arch/xtensa/esp32s3: Add qspi/spi_slave/lcd DMA request return value.
Optimize DMA initialization for duplicate calls.
2024-07-23 22:48:24 +08:00
Yanfeng Liu
3b9a346fe7 riscv/nsbi: unblock up_udelay
This fixes the always zero time in NuttSBI case as the `error` field
contains the correct timestamp. This in turn also fixes the block of
`up_udelay()` which further leads to boot failure of `canmv230:master`
config.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-07-22 23:46:43 +08:00
Inochi Amaoto
0ddcbe62ec arch/risc-v: does not clear IPI address in S mode
According to the riscv-aclint doc, writing 0 to SSWI address
has no effect. Remove this unnecessary write for S mode.

Link: https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-07-18 22:59:29 +08:00
YAMAMOTO Takashi
985d395b02 esp32s3_textheap.c: fix a build error w/o CONFIG_ESP32S3_SPIRAM 2024-07-18 16:42:52 +08:00
nuttxs
de3737cd90 arch/xtensa/esp32s3: Deinitialize ESP32-S3 QSPI GDMA engine.
Correctly releasing channels after using QSPI is crucial
to prevent issues caused by multiple requests that may lead
to DMA channel resource conflicts.
2024-07-18 13:41:04 +08:00
chao an
7780cfc5a6 tricore/cmake: add support of cmake build for tricore
Toolchain Upstream:
https://github.com/EEESlab/tricore-gcc-toolchain-11.3.0

CMake command:
$ cmake -B build -DBOARD_CONFIG=tc397/nsh -GNinja
$ cmake --build build

Signed-off-by: chao an <anchao@lixiang.com>
2024-07-18 13:40:49 +08:00
Inochi Amaoto
000b0ec4a1 arch/risc-v: make common up_allocate_heap weak symbol
The common `up_allocate_heap` is a strong symbol, which leads to
error when building with CONFIG_DEBUG_LINK_WHOLE_ARCHIVE. Make
`up_allocate_heap` weak function to mitigate this problem.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-07-18 13:40:37 +08:00
Lup Yuen Lee
bdf60d7966 risc-v/bl808, sg2000: Configure MMU to cache Kernel Text, Data and Heap (T-Head C906)
This PR configures the BL808 and SG2000 MMU (inside T-Head C906) to cache the the Kernel Text, Data and Heap.  We set the MMU Flags (Shareable, Bufferable and Cacheable) as explained in this article: https://lupyuen.github.io/articles/plic3#appendix-mmu-caching-for-t-head-c906

This PR fixes the Slow Memory Access for NuttX Kernel in BL808 and SG2000: https://github.com/apache/nuttx/issues/12696

In the next PR, we will fix the Slow Memory Access for NuttX Apps, by caching the User Text and Data.

arch/risc-v/src/bl808/bl808_mm_init.c: Added MMU Flags (Shareable, Bufferable and Cacheable) for BL808 Kernel Text, Data and Heap

arch/risc-v/src/sg2000/sg2000_mm_init.c: Added MMU Flags (Shareable, Bufferable and Cacheable) for SG2000 Kernel Text, Data and Heap
2024-07-17 12:08:04 -03:00
Yanfeng Liu
d6c67c555f riscv/trap: fix sp restore logic
This fixes stack pointer restore logic to avoid parent stack corruption
by forked child in PROTECTED build.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-07-17 17:20:00 +08:00
Yanfeng Liu
08c4686f47 riscv/fork: fix tp for PROTECTED
This fixes `tp` value of forked child in PROTECTED build to support
vfork. Why? the optimized `dispatch_syscall` requires `tp` to hold
the task TCB since commit e6973c764c.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-07-17 17:20:00 +08:00
chao an
4db1169e6f arch/tricore: fix compiler warning on GCC toolchain
tc3xx/tc3xx_timerisr.c: In function ‘up_timer_initialize’:
tc3xx/tc3xx_timerisr.c:58:39: warning: passing argument 1 of ‘tricore_systimer_initialize’ discards ‘volatile’ qualifier from pointer target type [-Wdiscarded-qualifiers]
   58 |   lower = tricore_systimer_initialize(&MODULE_STM0, 192, SCU_FREQUENCY);
In file included from tc3xx/tc3xx_timerisr.c:31:
nuttx/arch/tricore/src/common/tricore_internal.h:252:35: note: expected ‘void *’ but argument is of type ‘volatile Ifx_STM *’ {aka ‘volatile struct _Ifx_STM *’}
  252 | tricore_systimer_initialize(void *tbase, int irq, uint64_t freq);
      |                             ~~~~~~^~~~~
tc3xx/tc3xx_serial.c:177:16: warning: initialization discards ‘volatile’ qualifier from pointer target type [-Wdiscarded-qualifiers]
  177 |   .uartbase  = &MODULE_ASCLIN0,
      |                ^
tc3xx/tc3xx_serial.c:178:16: warning: initialization discards ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers]
  178 |   .pins      = &g_uart0_pins,
      |                ^
common/tricore_trapcall.c: In function ‘tricore_trapcall’:
common/tricore_trapcall.c:66:3: warning: passing argument 4 of ‘_assert’ discards ‘volatile’ qualifier from pointer target type [-Wdiscarded-qualifiers]
   66 |   PANIC_WITH_REGS("Trap", CURRENT_REGS);
      |   ^~~~~~~~~~~~~~~
In file included from common/tricore_trapcall.c:29:
nuttx/include/assert.h:189:45: note: expected ‘void *’ but argument is of type ‘volatile uintptr_t *’ {aka ‘volatile long unsigned int *’}
  189 |              FAR const char *msg, FAR void *regs);

Signed-off-by: chao an <anchao@lixiang.com>
2024-07-17 17:18:02 +08:00
chao an
8e20b8d862 arch/tricore: add support of tricore gcc toolchain
Toolchain Upstream:
https://github.com/EEESlab/tricore-gcc-toolchain-11.3.0

Signed-off-by: chao an <anchao@lixiang.com>
2024-07-17 17:18:02 +08:00
zouboan
b817db86b8 zynq-mpsoc: add support for mio/emio 2024-07-16 18:50:52 -03:00
chao an
bc7791e079 arch/tricore: synchronize instruction/data following MTCR/MFCR
Some barrier are necessary to avoid compiler optimizations

Signed-off-by: chao an <anchao@lixiang.com>
2024-07-16 21:13:13 +08:00
GC2020
8f243d3eb7 /rp2040 Rename the RP2040-specific PWM_MULTICHAN definition to avoid confusion with the global PWM_MULTICHAN 2024-07-16 20:09:10 +08:00
shizhenghui
fea727a050 arch/sim/Makefile: add openh264 & x264 include path
Signed-off-by: shizhenghui <shizhenghui@xiaomi.com>
2024-07-16 08:33:50 -03:00
shizhenghui
347864152d sim codec: add dependence to Kconfig
Signed-off-by: shizhenghui <shizhenghui@xiaomi.com>
2024-07-16 08:33:50 -03:00
shizhenghui
61f79757f7 v4l2m2m/sim encoder: move hostencoder to x264encoder
Signed-off-by: shizhenghui <shizhenghui@xiaomi.com>
2024-07-16 08:33:50 -03:00
shizhenghui
7248ba0293 sim decoder: update CMakeLists.txt
Signed-off-by: shizhenghui <shizhenghui@xiaomi.com>
2024-07-16 08:33:50 -03:00
shizhenghui
3675cfe585 v4l2m2m/sim decoder: rename hostdecoder to openh264dec
Signed-off-by: shizhenghui <shizhenghui@xiaomi.com>
2024-07-16 08:33:50 -03:00
Eren Terzioglu
0df037855a esp32[c3]: Add mcuboot build script for esp32c3-legacy 2024-07-16 10:30:56 +08:00
Eren Terzioglu
a9082e0882 esp32[s2]: Add nuttx toolchain support on mcuboot 2024-07-16 10:30:56 +08:00
Eren Terzioglu
c9f5ae5fa4 esp32[s3]: Add nuttx toolchain support on mcuboot 2024-07-16 10:30:56 +08:00
Eren Terzioglu
024e95875a esp32: Add nuttx toolchain support on mcuboot 2024-07-16 10:30:56 +08:00
Eren Terzioglu
553b1f5f5e esp32[c3|c6|h2]: Add nuttx toolchain support on mcuboot 2024-07-16 10:30:56 +08:00
adriendesp
baf52268cc arch/xmc4: Added pwm driver 2024-07-15 16:14:55 -03:00
Peter van der Perk
622b6d234a s32k1xx: FlexIO I2C master driver 2024-07-15 10:06:55 -03:00
Raman Gopalan
ef271b8fe2 at32uc3a0: Initial work for SimpleMachines' Mizar32-A 2024-07-15 20:46:41 +08:00
Yanfeng Liu
8bdc975abb riscv/cmake: fix Toolchain.cmake issue
This fixes the following issue when configuring canmv230:master
with Ubuntu stock toolchain and cmake 3.22:

```
CMake Error at .../arch/risc-v/src/cmake/Toolchain.cmake:218 (if):
  if given arguments:
    "STREQUAL" "GNU_RVG"
  Unknown arguments specified
```

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-07-15 19:41:03 +08:00