The eZ80F92 interrupt controller is very different from the eZ80F91. The eZ80F91 has:
1. Four byte interrupt vectors
2. The vector base address register is 16-bit so the vector table can lie in RAM
Whereas the eZ80F92 has:
1. Two byte interrupt vectors
2. An 8-bit vector base address
This means that the vectors must lie in the first 16-bits of FLASH and there must be a "trampoline" to get to interrupt handlers outside of the first 64-Kb of FLASH.
arch/z80/src/ez80/Toolchain.defs: Correct some CFLAGS when optimization suppressed.
arch/z80/src/ez80/Kconfig arch/z80/src/ez80/ez80_emac.c: Remove configuration option for selecting EMAC RAM address. This is duplicated and possibly conflicting. The correct address for the RAM is provided in the linker command file. The RAM should be configured once and using this single definitions.
arch/z80/src/ez80/ez80_startup.asm and arch/z80/src/ez80/ez80f9*_init.asm. Move RAM and FLAH intialization out of MCU-specific logic to common start-up logic. We cannot call any functions until SRAM is initialized and the stack is properly initialized because the return address is stored on the stack. Use internal SRAM for the IDLE stack to avoid the chicken'n'egg problem.
boards/z80/ez80/z20x/configs/sdboot/sdboot.zdsproj: Discuss build environments.
arch/z80/src/ez80/Toolchain.defs: Update some CFLAGS to match CFLAGS from ZDS-II IDE. Apparently, we must say that the CPU is an eZ80F91 event when compiler for eZ80F92.
boards/z80/ez80/z20x: Update linker scripts.
