The master clock frequency should be multiple of the sample rate
and bit clock at the same time. Then, check if the current master
clock satisfies such a condition and set it accordingly otherwise.
In order to gracefully stop the I2S stream, add an interface to set
a `streaming` status variable that sets the `AUDIO_APB_FINAL` flag
that will be handled by the upper layers of the audio subsystem.
According to RX/TX operation, the DMA descriptors (inlink/outlink)
should be set differently. When setting the inlink, the `suc_eof`
field must be cleared by software (it will be set by hardware when
a packet is received). Similarly, the `length` field will be set
by hardware a packet is received.
Define macros used to access the registers of the GDMA channels
according to the selected channel in the header file, enabling them
to be used by other drivers.
By splitting into two different functions the setup of the DMA
descriptors and the action of loading it to the GDMA outlink
register, it enables us to "cache" DMA descriptors ready to be send
and, then, just load them whenever we are able to actually send it.
The macro `SET_BITS` only sets the bits according to the bit mask
and, once it's being used to set the address field of the GDMA
inlink/outlink register, it's necessary to clean all the bits
corresponding to that field that were eventually setup previously
to avoid messing with the bits that correspond to the current
address being setup.
This option enables architecture-specific memory copy for dynamic code loading.
For example, Ambiq has MRAM regions for instruction which can't load by
the memcpy directly.
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
SiFive document: "ECC Error Handling Guide" states:
"Any SRAM block or cache memory containing ECC functionality needs to be
initialized prior to use. ECC will correct defective bits based on memory
contents, so if memory is not first initialized to a known state, then ECC
will not operate as expected. It is recommended to use a DMA, if available,
to write the entire SRAM or cache to zeros prior to enabling ECC reporting.
If no DMA is present, use store instructions issued from the processor."
Clean the cache at this early stage so no ECC errors will be flooding later.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Check that the base address and region size are properly aligned with
relation to each other.
With NAPOT encoding the area base and size are not arbitrary, as when
the size increases the amount of bits available for encoding the base
address decreases.
Implement the previously empty mpfs_ddr_rand with adapted "seiran128" code
from https://github.com/andanteyk/prng-seiran
This implements a non-secure prng, which is minimal in size. The DDR training
doesn't need cryptographically secure prng, and linking in the NuttX crypto
would increase the code size significantly for bootloaders.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Also move the DDRC clock enablement and reset to mpfs_init_ddr. This doesn't
change the functionality, but is the cleaner place for it.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Especially the write calibration must bail out if the memory test timeouts,
otherwise the device will get stuck in running the memory test in sequence,
and it will always timeout.
Negative error value was also not properly returned from mpfs_mtc_test.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
It doesn't make sense to try to auto-determine write latency, it may pass with too low value.
Keep the existing implementation if the write latency has been set to minimum
value, otherwise just set it.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Current implementation of QSPI in SPI mode was available only for MCUs
that do not have standard SPI at all. MCUs with both QSPI and SPI can
however also use QSPI in SPI mode and thus have one more SPI bus. This
commit adds required defines and config options to support QSPI in SPI
mode for all SAMv7 MCUs.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Calculate how long an I2C transation will take in microseconds, and use
this as the timeout for mpfs_i2c_sem_waitdone.
The reason for doing this is not to keep an i2c bus reserved for the full
1 second timeout, if e.g. a sensor is not on the bus / is faulty and
non-responsive. Reading the other sensors will be blocked for a relatively
long time (1 second) in this case. This fixes such behavior.
This commit adds function pwm_set_polarity() that setups channel
polarity based on input info from application layer.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Pinephone Pro port just nsh
Status:
booting till GICD / IRQ issue
style cleanups
start to fix style checks
revert offset
whitespaces
revert a64 bringup file
prob last cleanup
more cleanups
remove dts
move changes from a64 hardware specific folders to rk3399
undo common changes (except head.s)
revert gitignore
missing irq.h and rk3399_serial.c need to finish cleaning them up
WIP
add source for load address
make debug print hex again add board include
Pinephone Pro port just nsh
Status:
booting till GICD / IRQ issue
style cleanups
start to fix style checks
revert offset
whitespaces
revert a64 bringup file
prob last cleanup
more cleanups
remove dts
move changes from a64 hardware specific folders to rk3399
undo common changes (except head.s)
revert gitignore
missing irq.h and rk3399_serial.c need to finish cleaning them up
WIP
add source for load address
remove ccache, add board memory map
remove board reset
1 page might not be enough, if the task has a bigger stack. Best effort
is to allocate the default amount, however this won't work will all
tasks either.
Currently TX_FIFO_SIZE is not altered in mpfs_ep_set_fifo_size(),
but all paths (RX and TX) change MPFS_USB_RX_FIFO_SIZE only.
Fix the TX_FIFO_SIZE setup.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
