sergiotarxz/nuttx
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4 Commits

Author SHA1 Message Date
yf13
dec6ec1138 Update mode.h to add CSR_TVEC 2023-12-23 20:43:47 -08:00
Huang Qi
f93964ad3c riscv: Dump trap val in exception handler 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-08-30 14:55:33 +08:00
Xiang Xiao
e959775397 arch/riscv: Access [m|s]scratch through CSR_SCRATCH macro 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-02 14:08:37 +03:00
Ville Juven
c15b6701ce RISC-V: Implement option to run NuttX in supervisor mode (S-mode) 
- Add config "ARCH_USE_S_MODE" which controls whether the kernel
  runs in M-mode or S-mode
- Add more MSTATUS and most of the SSTATUS register definitions
- Add more MIP flags for interrupt delegation
- Add handling of interrupts from S-mode
- Add handling of FPU from S-mode
- Add new context handling functions that are not dependent on the trap
  handlers / ecall

NOTE: S-mode requires a companion SW (SBI) which is not yet implemented,
      thus S-mode is not usable as is, yet.
 2022-04-01 16:19:42 -03:00