Commit Graph

39002 Commits

Author SHA1 Message Date
YAMAMOTO Takashi
18b3b3f5c1 include/nuttx/streams.h: Appease nxstyle 2020-11-16 05:46:53 -08:00
YAMAMOTO Takashi
99c9a671d2 arch/arm/src/samd2l2/sam_start.c: Appease nxstyle 2020-11-16 05:46:53 -08:00
YAMAMOTO Takashi
23da936a38 arch/arm/src/nuc1xx/nuc_start.c: Appease nxstyle 2020-11-16 05:46:53 -08:00
YAMAMOTO Takashi
516d51d4d1 arch/arm/src/nrf52/nrf52_allocateheap.c: Appease nxstyle 2020-11-16 05:46:53 -08:00
YAMAMOTO Takashi
d007b37973 arch/arm/src/max326xx/common/max326_start.c: Appease nxstyle 2020-11-16 05:46:53 -08:00
YAMAMOTO Takashi
a86c58334c arch/arm/src/lpc54xx/lpc54_allocateheap.c: Appease nxstyle 2020-11-16 05:46:53 -08:00
YAMAMOTO Takashi
fd48419a3d arch/arm/src/kl/kl_start.c: Appease nxstyle 2020-11-16 05:46:53 -08:00
YAMAMOTO Takashi
b0e6462f6a arch/arm/src/lpc43xx/lpc43_allocateheap.c: Appease nxstyle 2020-11-16 05:46:53 -08:00
YAMAMOTO Takashi
cc2384ad8e z8: Appease nxstyle 2020-11-16 05:46:53 -08:00
YAMAMOTO Takashi
ba02387d68 hc12: Appease nxstyle 2020-11-16 05:46:53 -08:00
YAMAMOTO Takashi
638f31a42f hcs12: Appease nxstyle 2020-11-16 05:46:53 -08:00
Masayuki Ishikawa
13f3f84bae arch: armv7-a: Remove unnecessary d-cache operation in arm_cpustart.c
Summary:
- Remove unnecessary d-cache operation to make boot fast

Impact:
- armv7-a SMP only

Testing:
- Tested with sabre-6quad:smp (QEMU and dev board)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2020-11-16 00:53:17 -08:00
Masayuki Ishikawa
d15a6b4363 boards: sabre-6quad: Enable L2CC for smp/defconfig
Summary:
- This commit adds L2CC to smp/defconfig
- Also adds CLOCK_MONOTONIC

Impact:
- sabre-6quad:smp only

Testing:
- Tested with both QEMU and dev board

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2020-11-16 00:53:17 -08:00
Masayuki Ishikawa
3cc6ddd151 boards: sabre-6quad: Enable L2CC for nsh/defconfig
Summary:
- This commit adds L2CC to nsh/defconfig
- Also adds EXAMPLES_HELLO, TESTING_GETPRIME and TESTING_OSTEST

Impact:
- sabre-6quad:nsh only

Testing:
- Tested with both QEMU and dev board

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2020-11-16 00:53:17 -08:00
Masayuki Ishikawa
ad81db2272 arch: armv7-a: Fix arm_l2cc_pl310.c with DEBUGASSERT()
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2020-11-16 00:53:17 -08:00
Masayuki Ishikawa
649337b077 arch: imx6: Add arm_l2cc_pl310.c to Make.defs
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2020-11-16 00:53:17 -08:00
Masayuki Ishikawa
ab758664ed arch: imx6: Fix compile errors in chip.h
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>>
2020-11-16 00:53:17 -08:00
Masayuki Ishikawa
a813d27f5f arch: armv7-a: Fix comile errors in l2cc_pl310.h
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2020-11-16 00:53:17 -08:00
Masayuki Ishikawa
c52d83abc2 arch: armv7-a: Fix compile errors in arm_l2cc_pl310.c
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2020-11-16 00:53:17 -08:00
Masayuki Ishikawa
2039e2a565 arch: armv7-a: Fix style warnings in l2cc_pl310.h
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2020-11-16 00:53:17 -08:00
Masayuki Ishikawa
94b43b93e5 arch: armv7-a: Fix style warnings in arm_l2cc_pl310.c
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2020-11-16 00:53:17 -08:00
Brennan Ashton
8d02bce8e5 Disable smp selftest for bt_null driver
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
2020-11-15 22:26:25 +01:00
Nathan Hartman
08979d6e1a stm32/stm32_bbsram.c: Fix nxstyle errors
arch/arm/src/stm32/stm32_bbsram.h:

    * Fix nxstyle errors.
2020-11-15 20:42:55 +01:00
Frank-Christian Kruegel
bf5fa5557d Support for MAX1161X family of I2C 12 bit ADC chips:
MAX11612:  4 channels VCC=5V0 Int VRef=4.096V
MAX11613:  4 channels VCC=3V3 Int VRef=2.048V
MAX11614:  8 channels VCC=5V0 Int VRef=4.096V
MAX11615:  8 channels VCC=3V3 Int VRef=2.048V
MAX11616: 12 channels VCC=5V0 Int VRef=4.096V
MAX11617: 12 channels VCC=3V3 Int VRef=2.048V
Note: The chips' auto-scanning feature is not supported in this revision.
2020-11-15 05:59:01 -08:00
Xiang Xiao
e70bff723b board/sim: Remove the too strict warning
The variable shadow is a frequently-used feature
(especially in c++), so let's disable this warning

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-11-15 08:28:36 -03:00
YAMAMOTO Takashi
3ccbcf3c28 sim: Add a config to test libcxx 2020-11-15 08:28:36 -03:00
Xiang Xiao
b827565396 [libc++] Move the toolchain's macros undefinition to Make.defs
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-11-15 08:28:36 -03:00
Xiang Xiao
8bc4a5b08a [libc++] Cherry pick patches from mainline to fix warnings
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-11-15 08:28:36 -03:00
Masayuki Ishikawa
81abbcb75c boards: sabre-6quad: Add CONFIG_TESTING_GETPRIME=y to smp/defconfig
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2020-11-14 16:40:01 -08:00
Masayuki Ishikawa
064451b4ee Update TODO and sabre-6quad/README.txt regarding SMP
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2020-11-14 16:40:01 -08:00
Masayuki Ishikawa
a20463642e arch: armv7-a: Fix MMU settings for SDRAM in SMP mode
Summary:
- This commit fixes armv7-a deadlocks with D-cache in SMP mode.
- In SMP mode, MMU for SDRAM area must be set to shareable

Impact:
- SMP only

Testing:
- Tested with sabre-6quad:smp (QEMU and dev board)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2020-11-14 16:40:01 -08:00
Masayuki Ishikawa
812257d058 arch: armv7-a: Fix style warnings in mmu.h
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2020-11-14 16:40:01 -08:00
Masayuki Ishikawa
4cc38caba9 sched: Fix nx_waitid(), nx_waitpid(), nxtask_exithook() for SMP
Summary:
- I noticed waitpid_test stops with lc823450-xgevk:rndis
- The condition was CONFIG_DEBUG_ASSERTION=y
- Actually, the child task sent SIGCHILD but the parent couldn't catch the signal
- Then, I found that nx_waitid(), nx_waitpid() use sched_lock()
- However, a parent task and a child task are running on different CPUs
- So, sched_lock() is not enough and need to use a critical section
- Also, signal handling in nxtask_exithook() must be done in a critical section

Impact:
- SMP only

Testing:
- Tested with ostest with the following configurations
- lc823450-xgevk:rndis (CONFIG_DEBUG_ASSERTION=y and n)
- spresense:smp
- spresense:wifi_smp (NCPUS=2 and 4)
- sabre-6quad:smp (QEMU)
- esp32-core:smp (QEMU)
- maix-bit:smp (QEMU)
- sim:smp

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2020-11-14 16:31:49 -08:00
Bernd Walter
0cf66149ed twi_takesem() had been changed to return an int.
Neither the prototype, nor the description had been adapted, resulting in
compiler errors.
Fix both points.
2020-11-14 19:17:14 +01:00
Nathan Hartman
1aac3d7e57 stm32/stm32_aes.c: Fix nxstyle errors
arch/arm/src/stm32/stm32_aes.c:

    * Fix nxstyle errors.
2020-11-13 16:13:58 -08:00
Sara Souza
e6b6f06d22 xtensa/esp32: added support to automonitor by capture 2020-11-13 13:01:40 -03:00
YAMAMOTO Takashi
ca9bd8be0e Remove ARCROSSDEV leftovers
It has been removed while ago.
cf. 5efa93ec26
2020-11-13 05:54:20 -08:00
Dong Heng
bfb5214ef8 xtensa/esp32: Add SPI Flash hardware encryption I/O support 2020-11-13 08:37:59 +01:00
Nathan Hartman
4977522ead stm32: Add DMAMUX register mappings and request IDs
arch/arm/src/stm32/hardware/stm32_dmamux.h,
arch/arm/src/stm32/hardware/stm32g47xxx_dmamux.h:

    * New files, based on STM32G474RE reference manual, RM0440 Rev 4.
2020-11-13 08:09:10 +01:00
Nathan Hartman
35126b31b7 stm32f0l0g0/stm32_dmamux.h: Fix errors in bitfield definitions
Used reference manual for STM32G071CB. The F0 and L0 families do not
appear to have a DMAMUX.

arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h:

    * Remove all mentions of DMAMUX12 from comments. This family has
      at most DMAMUX1 only.

    * Add missing defines DMAMUX_CCR_SPOL_NONE,
      DMAMUX_CCR_SPOL_RISING, DMAMUX_CCR_SPOL_FALLING, and
      DMAMUX_CCR_SPOL_BOTH.

    * DMAMUX_CCR_SYNCID_SHIFT: Fix comment. Was "Bits 24-26" (3 bits)
      but datasheet shows bits 24-28 (5 bits).

    * DMAMUX_CCR_SYNCID_MASK: Fix mask. Was 0x7 (3 bits) but datasheet
      shows (5 bits) 0x1f.

    * DMAMUX1_CSR_SOF(x): Add parenthesis around macro parameter
      expansion.

    * DMAMUX1_CFR_SOF(x): Rename to DMAMUX1_CFR_CSOF(x) for
      consistency with datasheet and add parenthesis around macro
      parameter expansion.

    * DMAMUX_RGCR_GPOL_MASK: Fix incorrect mask. Was 0x7 (3 bits) but
      datasheet shows only 2 bits (0x3).

    * Add missing defines DMAMUX_RGCR_GPOL_NONE,
      DMAMUX_RGCR_GPOL_RISING, DMAMUX_RGCR_GPOL_FALLING, and
      DMAMUX_RGCR_GPOL_BOTH.

    * DMAMUX_RGCR_GNBREQ_SHIFT: Fix incorrect value. Was 17 (collision
      with DMAMUX_RGCR_GPOL_SHIFT) but datasheet and comment both show
      this bitfield at bits 19-23.

    * DMAMUX_RGCR_GNBREQL_MASK: Fix incorrect mask. Was 0x7 (3 bits)
      but datasheet shows 5 bits (0x1f).

    * DMAMUX1_RGSR_SOF(x): Rename to DMAMUX1_RGSR_OF(x) for
      consistency with datasheet and add parenthesis around macro
      parameter expansion.

    * DMAMUX1_RGCFR_SOF(x): Rename to DMAMUX1_RGCFR_COF(x) for
      consistency with datasheet and add parenthesis around macro
      parameter expansion.

    * DMAMAP_MAP(d,c): Add parenthesis around macro parameter
      expansion.

    * Fix nxstyle errors.
2020-11-12 23:07:37 -08:00
Nathan Hartman
fd020fa0ae stm32h7/stm32_dmamux.h: Add missing CCR SPOL defines
arch/arm/src/stm32h7/hardware/stm32_dmamux.h:

    * Add missing defines DMAMUX_CCR_SPOL_NONE,
      DMAMUX_CCR_SPOL_RISING, DMAMUX_CCR_SPOL_FALLING, and
      DMAMUX_CCR_SPOL_BOTH.

    * Fix nxstyle errors.
2020-11-13 08:03:02 +01:00
Simon Piriou
da70eb5c56 usbdev: adb: fix missing break 2020-11-12 21:35:07 -08:00
Simon Piriou
5892927aea board: add ADB example for stm32/photon 2020-11-12 21:35:07 -08:00
Peter Bee
1f5786f5ea libc/stdlib: Fix range check in strtoul(l)
The previous implementation of strtoul(l) is flawed. The range check
assumed that when overflow happens, the truncated value is smaller than
the original value. As a counter example, passing "10000000000" to
strtol will not trigger ERANGE, but return a truncated value. This patch
adds more accurate range checks.

Change-Id: I239e034e390b4974157ed6efa17110f2e74904cf
Signed-off-by: Peter Bee <bijunda1@xiaomi.com>
2020-11-12 06:01:33 -08:00
Nathan Hartman
87bfa24c8c stm32/stm32_spi: Add SPI register definitions for STM32G47XX
arch/arm/src/stm32/hardware/stm32_spi.h:

    * Avoid numerous ifdef on STM32 part numbers and make the
      different variations of SPI peripheral features more
      self-documenting: based on STM32_HAVE_IP_SPI_V* defines
      from chip.h, define some or all of HAVE_SPI_I2S,
      HAVE_SPI_TI_MODE, HAVE_SPI_ARB_DATA_SIZE, HAVE_SPI_FIFOS,
      HAVE_SPI_NSSP, HAVE_SPI_I2S_ASTRT, and make decisions on
      which registers and bitfields to define based on them.

    * Define registers and bitfields for STM32_HAVE_IP_SPI_V4,
      currently used only for STM32G47XX family MCUs, including
      SPI_CR1_CRCL, SPI_CR2_NSSP, SPI_CR2_FRXTH, SPI_CR2_LDMARX,
      SPI_CR2_LDMATX, SPI_CR2_DS_SHIFT/SPI_CR2_DS_MASK,
      SPI_SR_FRLVL_SHIFT/SPI_SR_FRLVL_MASK, and
      SPI_I2SCFGR_ASTRTEN.

    * SPI_I2SCFGR_I2SSTD_PHILLIPS: Was defined incorrectly as
      (xx << SPI_I2SCFGR_I2SSTD_SHIFT). Corrected this to
      (0 << SPI_I2SCFGR_I2SSTD_SHIFT).

    * SPI_I2SCFGR_I2SSTD_MSB: Was defined incorrectly as
      (0 << SPI_I2SCFGR_I2SSTD_SHIFT). Corrected this to
      (1 << SPI_I2SCFGR_I2SSTD_SHIFT).

    * Fix nxstyle errors.

arch/arm/include/stm32/chip.h:

    * Add new section "Peripheral IP versions" and specify version of
      SPI IP block for STM32F10XX, STM32F20XX, STM32F30XX, STM32F33XX,
      STM32F37XX, STM32F4XXX, STM32G47XX, and STM32L15XX.
2020-11-12 04:37:32 -08:00
Nathan Hartman
b63c0863b2 stm32h7/stm32_dmamux.h: Fix errors in bitfield definitions
arch/arm/src/stm32h7/hardware/stm32_dmamux.h:

    * DMAMUX1_CSR_SOF(x): Add parenthesis around macro parameter
      expansion.

    * DMAMUX1_CFR_SOF(x): Rename to DMAMUX1_CFR_CSOF(x) for
      consistency with datasheet and add parenthesis around macro
      parameter expansion.

    * DMAMUX_RGCR_GPOL_MASK: Fix incorrect mask. Was 7 (3 bits) but
      datasheet shows only 2 bits.

    * Add missing defines DMAMUX_RGCR_GPOL_NONE,
      DMAMUX_RGCR_GPOL_RISING, DMAMUX_RGCR_GPOL_FALLING, and
      DMAMUX_RGCR_GPOL_BOTH.

    * DMAMUX_RGCR_GNBREQ_SHIFT: Fix incorrect value. Was 17 (collision
      with DMAMUX_RGCR_GPOL_SHIFT) but datasheet and comment both show
      this bitfield at bits 19-23.

    * DMAMUX_RGCR_GNBREQL_MASK: Fix incorrect mask. Was 7 (3 bits) but
      datasheet shows 5 bits.

    * DMAMUX1_RGSR_SOF(x): Rename to DMAMUX1_RGSR_OF(x) for
      consistency with datasheet and add parenthesis around macro
      parameter expansion.

    * DMAMUX1_RGCFR_SOF(x): Rename to DMAMUX1_RGCFR_COF(x) for
      consistency with datasheet and add parenthesis around macro
      parameter expansion.

    * DMAMAP_MAP(d,c): Add parenthesis around macro parameter
      expansion.
2020-11-12 08:04:23 +01:00
Matias N
14d14bce05 pm.h: nxstyle fixes; change License to Apache (Greg and myself authors) 2020-11-12 08:01:25 +01:00
Matias N
13619ea0df nrf52: add SPI PM support (disable/enable SPI peripheral on sleep) 2020-11-12 08:01:25 +01:00
Matias N
a806ca9577 nrf52 SPI: rework support for undefined MOSI/MISO; add support for list DMA mode 2020-11-12 08:01:25 +01:00
Matias N
18be4198e1 Revert "nrf52_spi: support not defining MISO/MOSI pins"
This reverts commit e91a806ab6.
2020-11-12 08:01:25 +01:00