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Author SHA1 Message Date
Jiuzhu Dong
a91d143944 fs/unionfs: add sanity check for parameter 
if relpath is NULL, it will cause system crash:
unionfs_opendir with relpath NULL
    ->	unionfs_tryopendir
	    ->	unionfs_offsetpath
		->  strncmp(prefix, relpath, pfxlen

Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2022-04-01 16:35:43 +08:00
Jiuzhu Dong
e4c9a491c8 fs/unionfs: check return value to avoid unused value 
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2022-04-01 16:35:43 +08:00
Jiuzhu Dong
4631face24 fs/unionfs: fix bug about use after free about ui 
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2022-04-01 16:35:43 +08:00
zhouliang3
4e581f76f1 nuttx: Add "#include <nuttx/fs/ioctl.h>" to tioctl.h 
Signed-off-by: zhouliang3 <zhouliang3@xiaomi.com>
 2022-04-01 16:35:24 +08:00
YAMAMOTO Takashi
bc0ca51243 netdev_file_ioctl: Fix fcntl F_SETFL O_NONBLOCK regression 
This fixes a regression caused by the following commit,
which prevents the file flag from being updated.

```
commit 28860b5242
Author: chao.an <anchao@xiaomi.com>
Date:   Sat Mar 19 14:47:37 2022 +0800

    net/netdev: fix switch case missing break

    Signed-off-by: chao.an <anchao@xiaomi.com>
```

Note: some applications like mbedtls uses F_GETFL to confirm
the nonblock-ness of the socket. This is critical for such
applications.
 2022-04-01 16:35:12 +08:00
Jiuzhu Dong
37ef22b106 sigact: get free sigact from freelist always successful 
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2022-04-01 13:38:29 +08:00
ligd
40d9e10f37 rpmsgfs: use rptun_wait/post to resolve deadlock with usrsock 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2022-04-01 08:33:57 +03:00
ligd
96ed33f1d8 rpmsgfs: add timeout when mount in rpmsgfs 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2022-04-01 08:33:57 +03:00
ligd
023c54d0a4 rpmsgfs: add wait ready to rpmsgfs 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2022-04-01 08:33:57 +03:00
Petro Karashchenko
870ca12146 arch/risc-v: get wider visibility for arch instruction macros 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-04-01 10:31:24 +08:00
Ville Juven
e6d6734db2 ARCH_ADDRENV: Add guard against mis-configuration 
When process a is switched to process b, the address environment is
swapped with a call to group_addrenv(). The stack upon entry will be
a's, and upon exit b's. This will fail, so a neutral stack is required,
either a kernel stack or an IRQ stack.

Infrastructure for an IRQ stack is already in place, so give a hint
that an interrupt stack should be provided if address environments
are enabled.
 2022-04-01 02:02:10 +08:00
Jiuzhu Dong
840ba09b24 driver/syslog: Add microseconds after date time 
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2022-03-31 23:57:15 +08:00
wangbowen6
69e69740b5 mm_heap: heapsize align with MM_MIN_CHUNK. 
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
 2022-03-31 19:50:25 +08:00
wangbowen6
a0bde21f0f mm/mm_heap: place alloc-bit at the LSB of node->preceeding. 
Heap always allocate the memory at least 2bytes alignment.

Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
 2022-03-31 14:43:56 +03:00
Petro Karashchenko
44ee76dcbd arch/risc-v: fix ARCH_RV32 offset for the stub lookup table calculation 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-31 19:34:52 +08:00
Petro Karashchenko
36b0b95eb1 arch/risc-v: include csr.h indirectly through nuttx/irq.h 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-31 19:34:52 +08:00
Petro Karashchenko
5d856971db arch/risc-v: move REGLOAD/REGSTORE macro to riscv_internal.h 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-31 19:34:52 +08:00
Huang Qi
264e39e121 arch/risc-v: Remove unneeded group_addrenv call which handled by riscv_doirq 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-31 19:33:08 +08:00
Huang Qi
f72ca3db5c arch/risc-v: Dont' disable/enable irq in riscv_doirq 
Since these codes added to all chips but not fully tested,
so we should changd this behavior.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-31 19:33:08 +08:00
Huang Qi
32fe25278a arch/risc-v: Merge duplicated logic by riscv_doirq 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-31 19:33:08 +08:00
Huang Qi
a6c22b722f arch/risc-v: Remove deprecated logic from riscv_doirq 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-31 19:33:08 +08:00
Huang Qi
692ffb60b4 arch/risc-v: Rename up_doirq to riscv_doirq 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-31 19:33:08 +08:00
Huang Qi
814c07c792 arch/risc-v: Store/Restore FPU register in exception_common 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-31 11:49:36 +08:00
ligd
8db038c18a ioe_rpmsg: use rptun_wait/post to resolve deadlock with usrsock 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2022-03-31 01:37:49 +08:00
Huang Qi
379639a371 arch/risc-v/mpfs: Remove duplicated riscv_restorefpu 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-30 13:15:35 +03:00
Alin Jerpelea
38030b73f8 remove DISCLAIMER-WIP 
most licenses have been converted to Apache and the non Apache
licenses have been documented.
We can assume that now it should be the time to remove DISCLAIMER-WIP

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2022-03-30 16:16:25 +08:00
ligd
86a496d6ff rptun: forward panic/reset to lowerhalf 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2022-03-30 10:00:07 +03:00
ligd
bae9a97d31 openamp: add openamp patches 
0006-openamp-fix-scenario-case.patch
0007-openamp-divide-shram-to-TX-shram-RX-shram.patch
0008-rpmsg_virtio-don-t-need-check-status-when-get_tx_pay.patch

Signed-off-by: ligd <liguiding1@xiaomi.com>
 2022-03-30 10:00:07 +03:00
ligd
759898c090 rptun: add ping rpmsg support 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2022-03-30 10:00:07 +03:00
ligd
a19aef4d36 rptun: enable rx interrupts for virtq 
use wait_tx_buffer method need enable rx interrupts

Signed-off-by: ligd <liguiding1@xiaomi.com>
 2022-03-30 10:00:07 +03:00
ligd
1c7e59eafa rptun: pm_stay when send msg & pm_relax when all tx buffer returned 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2022-03-30 10:00:07 +03:00
ligd
f0ba2f0286 rptun: add rptun dump support 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2022-03-30 10:00:07 +03:00
ligd
5599f4e24a rptun: divide shram to TX & RX 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2022-03-30 10:00:07 +03:00
ligd
be49f6b87c rptun: add rpmsg_wait/post support for recursive dispatch 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2022-03-30 10:00:07 +03:00
ligd
7471d096cc rptun: add rptun_panic for both master & salve 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2022-03-30 10:00:07 +03:00
ligd
c9404e2705 rptun: use HPWORK instead of thread 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2022-03-30 10:00:07 +03:00
ligd
3ab7ade4ba rptun: add rptun_reset support 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2022-03-30 10:00:07 +03:00
ligd
7aba7c3790 rptun: add rptun_force_panic support 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2022-03-30 10:00:07 +03:00
ligd
5b6b748f6d rptun: set rptun thread default stack size to 4K 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2022-03-30 10:00:07 +03:00
田昕
4071f460b2 boards/boardctl:common boardctl to read reset cause. 
Signed-off-by: 田昕 <tianxin7@xiaomi.com>
 2022-03-30 09:59:10 +03:00
Jiuzhu Dong
ca8ce37433 fs/romfs: fix bug about compare path with same prefix 
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2022-03-30 09:04:57 +03:00
Alin Jerpelea
3ed4496a76 documentation: Add release notes for 10.3.0 release 
This is a local copy taken from the confluence notes
https://cwiki.apache.org/confluence/display/NUTTX/NuttX+10.3

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2022-03-30 11:19:52 +08:00
Gustavo Henrique Nihei
e1f28c19c2 arch/arm: Make CXX exception and RTTI depend on Kconfig options 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-30 11:19:29 +08:00
Gustavo Henrique Nihei
7b4d9f0afd esp32[s2/s3/c3]: Add defconfigs for testing C++ 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-30 11:19:29 +08:00
Gustavo Henrique Nihei
0bd436c8db libcxx: Fix libc++ for archs without conditional load/store support 
This commit brings a patch already merged to upstream LLVM project:
https://reviews.llvm.org/D118391

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-30 11:19:29 +08:00
Gustavo Henrique Nihei
8a215b60af libcxx: Add patch for preventing redefinition of PS macro on Xtensa 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-30 11:19:29 +08:00
Gustavo Henrique Nihei
06d0a9f1ad xtensa|risc-v: Make CXX exception and RTTI depend on Kconfig options 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-30 11:19:29 +08:00
Gustavo Henrique Nihei
a0617177e8 risc-v/esp32c3: Fix inclusion of C++ constructors/destructors table 
RISC-V GCC is configured with --enable-initfini-array so it emits an
.init_array section instead of .ctors

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-30 11:19:29 +08:00
Gustavo Henrique Nihei
c7311829e0 xtensa: Build OS-assisted atomic operations on ESP32-S2 
ESP32-S2 lacks support for conditional load/store instructions.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-30 11:19:29 +08:00
Gustavo Henrique Nihei
7926bce26b xtensa: Move XCHAL_SWINT_CALL definition into syscall header 
This is required to avoid the interface header (syscall.h) depending on
the xtensa_swi.h header from the implementation

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-30 11:19:29 +08:00