Commit Graph

5 Commits

Author SHA1 Message Date
Alin Jerpelea
222a3b9fe8 arch: arm: cxd56xx: nxstyle fixes
nxstyle fixes for cxd56xx

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2020-04-14 13:20:21 +01:00
Alin Jerpelea
2be1153030 Merged in alinjerpelea/nuttx (pull request #1061)
boards: cxd56xx: spresense: cleanup and new defconfig

* arch: cxd56xx: remove NVIC_SYSH redefinition

    The NVIC_SYSH is already defined in nvicpri.h

    Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>

* boards: cxd56xx: spresense: configs: enable SPRESENSE_EXTENSION

    Enable high current mode for the Spresense Extension board on all examples
    that have SDCARD support

    Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>

* boards: cxd56xx: spresense: ifdef SDCARD_TXS02612

    The SD Card TXS02612 port expander is hosted on the Extension board and
    should not be enabled if the extension board is not prezent.

    Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>

* boards: cxd56xx: spresense: configs: increase MQ_MAXMSGSIZE

    This change is needed by the display driver on spresense platform

    Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>

* boards: cxd56xx: spresense: config: add lcd examples defconfig

    This is a configuration for the basic nx examples

    Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>

Approved-by: Gregory Nutt <gnutt@nuttx.org>
2019-10-24 14:26:02 +00:00
Gregory Nutt
0ed1a06016 arch/arm/include/cxd56xx/chip.h: The correction of commit c300f27130 must be applied to the CXD56xx too. 2019-08-10 08:33:47 -06:00
Gregory Nutt
545cfada38 This commit removes CONFIG_ARCH_INT_DISABLEALL. In the normal course of things, interrupts must occasionally be disabled using the up_irq_save() inline function to prevent contention in use of resources that may be shared between interrupt level and non-interrupt level logic. Now the question arises, if we are using BASEPRI to disable interrupts and have high priority interrupts enabled (CONFIG_ARCH_HIPRI_INTERRUPT=y), do we disable all interrupts except SVCall (we cannot disable SVCall interrupts). Or do we only disable the "normal" interrupts?
If we are using the BASEPRI register to disable interrupts, then the answer is that we must disable ONLY the "normal interrupts".  That is because we cannot disable SVCALL interrupts and we cannot permit SVCAll interrupts running at a higher priority than the high priority interrupts (otherwise, they will introduce jitter in the high priority interrupt response time.)

Hence, if you need to disable the high priority interrupt, you will have to disable the interrupt either at the peripheral that generates the interrupt or at the NVIC.  Disabling global interrupts via the BASEPRI register cannot effect high priority interrupts.
2019-08-09 10:52:35 -06:00
Nobuto Kobayashi
eba004d498 arch/arm/src/cxd56xx and arch/arm/include/cxd56xx: Add initial CXD56xx chip sources. 2019-04-22 07:51:22 -06:00