Commit Graph

9 Commits

Author SHA1 Message Date
lipengfei28
c25f839b06 pci: add pci bus find capability interface
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-09-06 10:01:11 +08:00
lipengfei28
45f1597562 pci: add pci read/write config/io space interface
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-09-06 10:01:11 +08:00
lipengfei28
d9c8838319 pci: use g_pci_ctrl_list replace g_root_bus_list
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-09-06 10:01:11 +08:00
yangshuyong
75f8c72dbb drivers/pci/pci_qemu_edu: update qemu edu driver code
Signed-off-by: yangshuyong <yangshuyong@xiaomi.com>
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-09-06 10:01:11 +08:00
yangshuyong
9c07b369e9 drivers/pci/pci_qemu_test: update qemu pci test code
Change the qmeu pci test code for new pci driver framework

Signed-off-by: yangshuyong <yangshuyong@xiaomi.com>
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-09-06 10:01:11 +08:00
yangshuyong
7cbb7d36d8 Changed the x86 64 pci driver
Signed-off-by: yangshuyong <yangshuyong@xiaomi.com>
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-09-06 10:01:11 +08:00
yangshuyong
125884ae95 Changed the pci bus for arm architecture
Signed-off-by: yangshuyong <yangshuyong@xiaomi.com>
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-09-06 10:01:11 +08:00
raiden00pl
a12fdd8876 cosmetic changes after pci code rebase 2024-01-25 09:09:30 -08:00
Brennan Ashton
69ed5bb67d Various fixes for PCI work
Squashed commits:

1. Porting prior PCI work in place of jailhouse code

At this point the PCI enumeration works for x86_64 including over
pci-pci bridges.

Running QEMU with this configuration we see the bridge and the
device on the bridge.  It also detected the qemu test device

qemu-system-x86_64 \
  -cpu host,+pcid,+x2apic,+tsc-deadline,+xsave,+rdrand \
  --enable-kvm -smp 1 -m 2G -cdrom boot.iso --nographic -no-reboot \
  -device pci-testdev \
  -device pci-bridge,id=bridge0,chassis_nr=2 \
  -device e1000,bus=bridge0,addr=0x3

qemu_pci_init: Initializing PCI Bus
pci_probe_device: [00:00.0] Found 8086:1237, class/revision 06000002
pci_probe_device: [00:01.1] Found 8086:7010, class/revision 01018000
pci_probe_device: [00:01.2] Found ffff:ffff, class/revision ffffffff
pci_probe_device: [00:01.3] Found 8086:7113, class/revision 06800003
pci_probe_device: [00:01.4] Found ffff:ffff, class/revision ffffffff
pci_probe_device: [00:01.5] Found ffff:ffff, class/revision ffffffff
pci_probe_device: [00:01.6] Found ffff:ffff, class/revision ffffffff
pci_probe_device: [00:01.7] Found ffff:ffff, class/revision ffffffff
pci_probe_device: [00:02.0] Found 1234:1111, class/revision 03000002
pci_probe_device: [00:03.0] Found 8086:100e, class/revision 02000003
pci_probe_device: [00:04.0] Found 1b36:0005, class/revision 00ff0000
pci_probe_device: [00:04.0] Probing
pci_check_pci_bridge: [00:05.0] Found Bridge
pci_probe_device: [01:03.0] Found 8086:100e, class/revision 02000003
pci_probe_device: [00:05.0] Found 1b36:0001, class/revision 06040000

2. Remove unused CONFIG_PCI_MAX_BDF option

3. Add a workaround for Jailhouse pci scanning

4. Extend BAR parsing and handle PIO and MMIO for pci-testdev

Signed-off-by: Brennan Ashton <bashton@brennanashton.com>

5. PCI: Add initial support for QEMU 'edu' test device

Signed-off-by: Brennan Ashton <bashton@brennanashton.com>

6. Bring up PCI later in boot process

Signed-off-by: Brennan Ashton <bashton@brennanashton.com>

7. Add ISR and DMA support to QEMU edu test pci device

Signed-off-by: Brennan Ashton <bashton@brennanashton.com>

8. Fix bad function prototype definition in qemu_edu

9. intel64:  Add a pci test configuration and instructions

Signed-off-by: Brennan Ashton <bashton@brennanashton.com>

10. PCI: Fix issue in identification of 64bit bar

Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
2024-01-25 09:09:30 -08:00