Abdelatif Guettouche
a7d8d9dd98
esp32s2/tie.h: Run the file though detab.
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Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-10-14 07:39:54 -03:00
Abdelatif Guettouche
6d246eb18f
esp32s2/tie.h: The old tie.h file was from ESP32 which doesn't apply to
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ESP32-S2. This commit gets the correct S2 tie.h file
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-10-14 07:39:54 -03:00
zhuyanlin
9ea7676731
arch:xtensa: rename XCHAL_INT_NLEVELS to XCHAL_NUM_INTLEVELS
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The name used in Tensilica support file core-isa.h for all vendors is
`XCHAL_NUM_INTLEVELS`.
Use a new name may be confused by newer porting xtensa arch.
Change-Id: Ie108d3fdfcc02c81f0eacfca852a1cfc9eea17de
2021-08-28 21:51:45 +02:00
Alan C. Assis
929a4a7278
Fix dangling whitespace at the end of line
2021-06-01 07:49:54 +02:00
Alan C. Assis
06795a221a
Clean ESP32S2 Xtensa files
2021-06-01 07:49:54 +02:00
Abdelatif Guettouche
fccd5fbdd2
esp32s2_allocateheap.c: Use the address of the ROM data from the ROM linker script.
2021-06-01 07:49:54 +02:00
Alan C. Assis
7767acd24a
Add initial ESP32S2 Xtensa support
2021-06-01 07:49:54 +02:00
