RAM is expected to start from 0x08000000, not from
0x80000000 in this case. DDR starts from 0x80000000.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Polarfire Icicle board has only (128K - 256) bytes for the bootloader
in the non-volatile eNVM. This space is barely enough for running NuttX.
If OpenSBI is selected, it will be placed in DDR. This all means the
nuttx.bin file grows into gigabyte size, filling the unused space (ddr -
envm) with zeroes.
The memory layout is as follows:
MEMORY
{
ddr (rx) : ORIGIN = 0x80000000, LENGTH = 4M
envm (rx) : ORIGIN = 0x20220100, LENGTH = 128K - 256
l2lim (rwx) : ORIGIN = 0x08000000, LENGTH = 1024k
l2zerodevice (rwx) : ORIGIN = 0x0A000000, LENGTH = 512k
}
OpenSBI library is used as a separate binary, which is stored into
eMMC or SD-card. It is then loaded into its precise location in DDR.
Thus, we separate OpenSBI from NuttX and end up with two images
by utilizing the objcopy options:
--only-section=sectionpattern (-j in short)
--remove-section=sectionpattern (-R in short)
This is only valid when CONFIG_MPFS_OPENSBI is set.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Add a pinmap header for mpfs to be able to configure MSSIO GPIOs
This also adds Kconfigs for some different chip/package types of the PolarFire SOC
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
This fixes problems with DDR training sequence on aries m100pfs board
- Set LIBERO_SETTING_RPC_ODT_* to 6, which matches 40 ohm. Originally it was 120 ohm (2)
- Set BCLKSCLK_OFFSET value to 5, which matches icicle board setting
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Update the cache settings for the Aries m100pfsevp board. This
assigns scratchpad ways for this board as well, as seen in the
commit 491ae6c.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
OpenSBI may be compiled as an external library. OpenSBI commit d249d65
(Dec. 11, 2021) needs to be reverted as it causes memcpy / memcmp to
end up in the wrong section. That issue has yet no known workaround.
OpenSBI may be lauched from the hart0 (e51). It will start the U-Boot
and eventually the Linux kernel on harts 1-4.
OpenSBI, once initialized properly, will trap and handle illegal
instructions (for example, CSR time) and unaligned address accesses
among other things.
Due to size size limitations for the mpfs eNVM area where the NuttX
is located, we actually set up the OpenSBI on its own section which
is in the bottom of the DDR memory. Special care must be taken so that
the kernel doesn't override the OpenSBI. For example, the Linux device
tree may reserve some space from the beginning:
opensbi_reserved: opensbi@80000000 {
reg = <0x80000000 0x200000>;
label = "opensbi-reserved";
};
The resulting nuttx.bin file is very large, but objcopy is used to
create the final binary images for the regions (eNVM and DDR) using
the nuttx elf file.
Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Assign ways to L2 zerodevice. L2 zero device is used for
the scratchpad functionality. The area may be used for the
harts communicating to each other.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
src/mpfs_emmcsd.c: In function 'mpfs_board_emmcsd_init':
Error: src/mpfs_emmcsd.c:72:40: error: 'SDIO_SLOTNO' undeclared (first use in this function)
finfo("Initializing SDIO slot %d\n", SDIO_SLOTNO);
^~~~~~~~~~~
src/mpfs_emmcsd.c:72:40: note: each undeclared identifier is reported only once for each function it appears in
Error: src/mpfs_emmcsd.c:83:55: error: 'SDIO_MINOR' undeclared (first use in this function); did you mean 'SHRT_MIN'?
finfo("Bind SDIO to the MMC/SD driver, minor=%d\n", SDIO_MINOR);
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
- Add defconfig and board specific files
- Create mpfs/common for code which is shared between MPFS boards.
- Add support for GPIO driven EMMCSD mux.
- Move DDR Libero definitions from arch to boards.
Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>
E51 may configure the L1 and L2 caches. Once configured,
no reconfiguration is possible after hardware reset is
issued.
L2 is 16-way set associative with write-back policy. The
size 2 MB, from which 1 MB is utilized with the values
provided here. That's a total of 8 ways. The rest of the
L2 is left out for the bootloader usage.
mpfs_enable_cache() first checks the bootloader usage
doesn't overlap with the cache itself, thus providing a
set of functional values.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
This adds DDR training. The training has a small chance of failing,
and then the training is restarted.
DDR training cannot be done meaningfully while the software is
in DDR. If the system is intended to run from eNVM, like a
bootloader, the linker script should be tuned to utilize the envm
region as follows:
envm (rx) : ORIGIN = 0x20220100, LENGTH = 128K - 256
l2lim (rwx) : ORIGIN = 0x08000000, LENGTH = 1024k
256 bytes are reserved for the system; The fixed block may be
installed from the 'hart-software-services' -repository:
https://github.com/polarfire-soc/hart-software-services.git
For example, the 256-byte image: hss-envm-wrapper-bm1-dummySbic.bin
may be prepended on the nuttx bootloader image in the following
manner:
cat hss-envm-wrapper-bm1-dummySbic.bin > nuttx_bootloader.bin
cat nuttx.bin >> nuttx_bootloader.bin
riscv64-unknown-elf-objcopy -I binary -O ihex --change-section-lma
*+0x20220000 nuttx_bootloader.bin flashable_image.hex
This provides an image 'flashable_image.hex' that may be flashed on
the eNVM region via Microsemi Libero tool.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Add a driver for CorePWM block, which can be instantiated on PolarFire SOC FPGA
This supports 2 CorePWM blocks on the FPGA. One CorePWM block provides 8 PWM output signals
