Update internal reference to get the most updated Espressif's
libraries. Those libraries are based on branch `release/v5.1` of
the ESP-IDF and include `v5.1.4` version of it.
In a multicore task scenario, there may be a situation where the task runs on different cores at different time slices (when the task is not bound to a particular core).
When the task calls cache clean/flush(range > cache size), depending on the optimization, clean_all, flush_all are called. however, at this point, there may be dirty data or incomplete data profiles in the cache on the kernel that is running the task, which may result in dirty data being flushed into memory or make the application think that the flushed data should be successfully flushed into memory, leading to unknown consequences.
Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
arch/xtensa/src/esp32s3/hardware/esp32s3_sdmmc.h|esp32s3_soc.h,
boards/xtensa/esp32s3/common/include/esp32s3_board_sdmmc.h,
boards/xtensa/esp32s3/common/src/Make.defs|esp32s3_board_sdmmc.c,
boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_bringup.c: add SD/mmc driver
Support 1-bit bus width and 4-bit bus width. Support eMMC high speed SDR mode.
Support transfer data with DMA. Support SD clock frequency up to 40MHZ.
Signed-off-by: Yinzhe Wu <Yinzhe.Wu@sony.com>
Reviewed-by: Yuezhang Mo <Yuezhang.Mo@sony.com>
Reviewed-by: Jacky Cao <Jacky.Cao@sony.com>
Tested-by: Yinzhe Wu <Yinzhe.Wu@sony.com>
Enabling CONFIG_PRIORITY_INHERITANCE config causes a build error
Based on Nuttx OS reserve memory for mutex struct.
Pass build based on
- CONFIG_PRIORITY_INHERITANCE y
- CONFIG_SEM_PREALLOCHOLDERS 0/8
1. For some reasons, the bootloader will set CPU source to BBPLL and enable it,
but there are calibration issues, so we need turn off the BBPLL and do calibration again to fix the issue.
2. Corresponding issue link: 89cc9084ab
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
Other ESP32-S3 modules (with embedded flash and PSRAM) were added.
Also, the `help` section of the Kconfig was updated to better
describe the modules' flash and PSRAM sizes.
Provide `up_copy_section` function that enables copying data using
the data bus. If the memory destination address is accessible
through the instruction bus, the data is copied using the
correspondent address accessible through the data bus.
The buffer initialization function (`i2s_buf_initialize`) calls
`i2s_buf_free`, which performs buffer initialization within a
critical section (`spin_lock_irqsave`). If this function is called
under the same critical section (same spinlock), initialization
will hang.
arch/xtensa: add support for capture driver on ESP32 and ESP32|S3|
Squashed:
Initial settings for MCPWM Capture on board level
Created lower half files - compilation ok
Using capture debug features. Simple example on fops works
Successful duty and freq calculation
Documentation update
Fixed and added interupt capabilities for all 3 capture channels
Cleaned defconfig
Renamed macros, added S3 options and moved arch source to common dir
Added support for ESP32S3
Added capture example to defconfig and renamed
Basic bring up ready. New Kconfig options for motor.
Good motor registration
Working on enabling pwm generators
Working on enabling pwm generators
Added fops functions
Success on PWM 50%
stable pwm operation for bdc
Added loopback option for testing
Improved rules on fsm
Working motor direction control
Testing new ISR for fault handling
Issues on fault ISR
Removed fault implementation (not working)
Added support for esp32s3
Documentation improvements
Added default motor spin direction
Added parameter change while running
Review fixes
arch/xtensa: add support for fault signal on motor control
Squashed:
Initial settings for MCPWM Capture on board level
Created lower half files - compilation ok
Using capture debug features. Simple example on fops works
Successful duty and freq calculation
Documentation update
Fixed and added interupt capabilities for all 3 capture channels
Cleaned defconfig
Renamed macros, added S3 options and moved arch source to common dir
Added support for ESP32S3
Added capture example to defconfig and renamed
Basic bring up ready. New Kconfig options for motor.
Good motor registration
Working on enabling pwm generators
Working on enabling pwm generators
Added fops functions
Success on PWM 50%
stable pwm operation for bdc
Added loopback option for testing
Improved rules on fsm
Working motor direction control
Testing new ISR for fault handling
Issues on fault ISR
Removed fault implementation (not working)
Added support for esp32s3
Documentation improvements
Added default motor spin direction
Added parameter change while running
Got responsive fault indicator
Working brakes - still need to work on starting isr
Fixed single-time ISR initializiation
Working soft brake on fault
Improved KConfig for BDC and BLDC
Kconfig fixed at board level
when the thread to backtrace is exiting, get_tcb and up_backtrace in
different critical section may cause try to dump invalid pointer, have
to ensure the nxsched_get_tcb and up_backtrace inside same critical
section procedure.
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
Correctly releasing channels after using QSPI is crucial
to prevent issues caused by multiple requests that may lead
to DMA channel resource conflicts.
This compilation flag was added in the same way as done for esp32
in order to avoid unexpected behaviors when accessing registers
using struct bitfields.
Signed-off-by: Almir Okato <almir.okato@espressif.com>
The Simple Boot feature for Espressif chips is a method of booting
that doesn't depend on a 2nd stage bootloader. Its not the
intention to replace a 2nd stage bootloader such as MCUboot and
ESP-IDF bootloader, but to have a minimal and straight-forward way
of booting, and also simplify the building.
This commit also removes deprecated code and makes this bootloader
configuration as default for esp32 targets and removes the need
for running 'make bootloader' command for it.
Signed-off-by: Almir Okato <almir.okato@espressif.com>
Move and unify map_rom_segments function called when starting
Simple Boot and MCUboot compatible images.
Signed-off-by: Almir Okato <almir.okato@espressif.com>
This current driver does not handle well netpkts used in the
write buffers.
I learned about this document:
https://github.com/apache/nuttx/blob/master/Documentation/components/net/netdriver.rst
After I ported and contributed the original driver.
However from the document, I understand these types of drivers are
simpler to implement and I could simplify the driver and handle
correctly the TCP write buffers.
Only in the non-critical region， nuttx can the respond to the irq and not hold the lock
When returning from the irq, there is no need to check whether the lock needs to be restored
test:
We can use qemu for testing.
compiling
make distclean -j20; ./tools/configure.sh -l qemu-armv8a:nsh_smp ;make -j20
running
qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic -machine virt,virtualization=on,gic-version=3 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx
Signed-off-by: hujun5 <hujun5@xiaomi.com>
When the PSRAM is enabled, we should not allocate the TX/RX
buffers there, so we use kmm_calloc here, to make it into IRAM,
so the ethernet controller can read bytes from it.
Squashed:
Initial settings for MCPWM Capture on board level
Created lower half files - compilation ok
Using capture debug features. Simple example on fops works
Successful duty and freq calculation
Documentation update
Fixed and added interupt capabilities for all 3 capture channels
Cleaned defconfig
Renamed macros, added S3 options and moved arch source to common dir
Added support for ESP32S3
Added capture example to defconfig and renamed
For now, IOB off-loading in the wireless driver was removed because
it is not compatible with SMP-enabled devices, which is valid for
ESP32-S3. The performance gain by keeping the IOB off-loading in
the wireless drivers is not exceeded by keeping the flat buffer
approach and enabling `CONFIG_SMP=y`.
Use `nxsched_gettid` instead of `nxsched_getpid`. Previously each
kernel thread was modelled as a task, so the pid is the same of the
kthread id. Now, with shared kthread group (introduced by #12320),
the pid of all kthreads will be 0 by design in shared group.
cpu0 cpu1:
user_main
signest_test
sched_unlock
nxsched_merge_pending
nxsched_add_readytorun
up_cpu_pause
arm_sigdeliver
enter_critical_section
Reason:
In the SMP, cpu0 is already in the critical section and waiting for cpu1 to enter the suspended state.
However, when cpu1 executes arm_sigdeliver, it is in the irq-disabled state but not in the critical section.
At this point, cpu1 is unable to respond to interrupts and
is continuously attempting to enter the critical section, resulting in a deadlock.
Resolve:
adjust the logic, do not entering the critical section when interrupt-disabled.
test:
We can use qemu for testing.
compiling
make distclean -j20; ./tools/configure.sh -l qemu-armv8a:nsh_smp ;make -j20
running
qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic -machine virt,virtualization=on,gic-version=3 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx
Signed-off-by: hujun5 <hujun5@xiaomi.com>
As suggested in PR:12530, changed the default names of ESP32S3WROOM chips to ESP32S3WROOM1N4,
ESP32S3WROOM2N16R8, ESP32S3WROOM2N32R8, ESP32S3MINI1N8.
Also regenerated all the defconfigs for board configurations.
Added a custom ESP32S3 module for custom flash configurations.
Declared ESP32S3_PSRAM_8M variable with prompt
* arch/risc-v/src/common/Toolchain.defs
arch/xtensa/src/lx6/Toolchain.defs
arch/xtensa/src/lx7/Toolchain.defs
- Define SHMODULEFLAGS etc. for sotest/dynload
- Add --entry=__start to SHMODULEFLAGS
* boards/arm64/qemu/qemu-armv8a/scripts/Make.defs
boards/sim/sim/sim/scripts/Make.defs
- Define SHMODULEFLAGS etc. for sotest/dynload
This commit enables users to select the legacy bootloader (IDF
bootloader) in `menuconfig` directly. Please note, that this is a
legacy option intended to support devices already deployed and it
isn't recommended for new designs.
The Simple Boot feature for Espressif chips is a method of booting
that doesn't depend on a 2nd stage bootloader. Its not the
intention to replace a 2nd stage bootloader such as MCUboot and
ESP-IDF bootloader, but to have a minimal and straight-forward way
of booting, and also simplify the building.
This commit also removes deprecated code and makes this bootloader
configuration as default for esp32s2 targets and removes the need
for running 'make bootloader' command for it.
Signed-off-by: Almir Okato <almir.okato@espressif.com>
