Commit Graph

21624 Commits

Author SHA1 Message Date
Jukka Laitinen
dae31dc866 arch/risc-v/src/mpfs/mpfs_i2c.c: Clear I2C_CTRL bits when initializing/deinitializing bus
Ensure that there are no pending state or interrupts in the i2c controller. This removes
errors caused by deinitialize/initialize sequences in error cases.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-02-06 08:52:31 -08:00
Eero Nurkkala
bcf7aa4b63 risc-v/mpfs: i2c: perform sanity checks
Replace risky DEBUGASSERT()s with real sanity checks. Also,
do a few more checks as the system might occasionally fire an
interrupt if the system has been restarted while in middle of
an i2c transaction.

Yet, modify i2c_transfer() function so that up_disable_irq()
is always called at the end to better prevent ill-timed irqs.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2024-02-06 08:52:31 -08:00
Eero Nurkkala
b0cef9e008 risc-v/mpfs: i2c: prevent out of bounds read access
priv->msgid may grow past its boundaries, causing
struct i2c_msg_s *msg = &priv->msgv[priv->msgid]
to read data out of boundaris.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2024-02-06 08:52:31 -08:00
Rdk-T
7f01db30dc Add EtherCAT support on xmc4800-relax. 2024-02-05 22:23:30 -08:00
SPRESENSE
a303ec8653 arch: cxd56xx: Add new feature to use GNSS RAM
As long as the GNSS feature is not used, GNSS RAM can be used as general memory.
This memory is 640KByte total, which is lower performance than the application RAM.
It is possible to locate text, data and bss into GNSS RAM and to use as heap area.
2024-02-05 05:53:51 -08:00
SPRESENSE
fc5ae43dda arch: cxd56xx: Add function to control GNSS RAM clock
Add function to enable and disable GNSS RAM clock.
2024-02-05 05:53:51 -08:00
SPRESENSE
1b3b12ed00 arch: cxd56xx: update loader and gnssfw version
Update loader and gnssfw to version 2.2.20591
2024-02-05 05:53:51 -08:00
Adam Comley
399cd88e7f Support RP2040 Clock Outputs 2024-02-04 16:51:53 -08:00
Xiang Xiao
ebc6924b26 risc-v/mpfs: Remove thee unused seq[s|m] fields
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2024-02-04 09:54:05 +01:00
Xiang Xiao
1e3914ec9d rptun: Remove the unused shmemname field and argument
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2024-02-04 09:54:05 +01:00
Xiang Xiao
6a6bd30500 rptun: Remove the empty implementation of get_firmware and get_addrenv
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2024-02-04 09:54:05 +01:00
Xiang Xiao
43d51cd4fc arch: Remove the identity mapping of up_addrenv_va_to_pa and up_addrenv_pa_to_va
and reuse the reuse the implementation from:
drivers/misc/addrenv.c

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2024-02-04 09:54:05 +01:00
Yanfeng Liu
73ecd741e7 risc-v/common: add param to mmu_flush_cache interface
Current mmu_flush_cache() hook lacks the reg param which needed by
some targets. So this PR adds the param and update existing targets
using that hook.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-02-03 22:05:42 -08:00
Tomáš Pilný
3e85c1886e esp32/dac-one-shot: lower-half driver for ESP32 internal DAC
Enable with ./tools/configure.sh -l esp32-devkitc:dac
DAC channel 0 = GPIO 25
DAC channel 1 = GPIO 26
default path: /dev/dac0

Resolution 8 bits = values 0~255
Voltage: 0~Vref

The reference voltage 'Vref' here is input from the pin VDD3P3_RTC
which ideally equals to the power supply VDD (3.3V).
2024-02-02 09:23:28 -08:00
Ville Juven
8e4b2e8a2a arch/arm_addrenv_pgmap.c: Add minimal page map implementation for ARM 2024-02-02 09:09:55 -08:00
Ville Juven
15f19c32ac arch/addrenv: Add utility function to wipe one page
up_addrenv_page_wipe can be used to wipe a single page of memory.
2024-02-02 09:09:55 -08:00
Yanfeng Liu
6594439271 risc-v/nuttsbi: fix weak sbi_late_initialize issues
Weak function sometimes can't have strong implementation linked.
This patch uses NUTTSBI_LATE_INIT config and normal function instead
to avoid those issues.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-02-01 21:26:16 -08:00
Jari Nippula
e40b66bd6f risc-v/mpfs: wrapper for sdio device drivers
Additional mpfs_sdio layer on top of mpfs_emmcsd and mpfs_coremmc
block device drivers to let both block devices be enabled at the
same time.
2024-02-01 02:07:32 -08:00
Yanfeng Liu
dbe42db611 arch/Kconfig: replace RPTUN_PING with RPMSG_PING
The RPTUN_PING option has been replaced by RPMSG_PING but this
use for PERF_EVENTS is left behind, so replace it here as well.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-02-01 16:50:23 +08:00
Eren Terzioglu
d1db1810ad risc-v/espressif: Rename espressif/esp32c3 as esp32c3
risc-v/espressif: Rename espressif/esp32c6 as esp32c6
risc-v/espressif: Rename espressif/esp32h2 as esp32h2
2024-01-30 08:32:05 +01:00
Eren Terzioglu
c8d7c81cb9 risc-v/esp32c3: Rename legacy approach esp32c3 as esp32c3-legacy 2024-01-30 08:32:05 +01:00
Eren Terzioglu
4c4d62ff93 Rename espressif folder as common/espressif 2024-01-30 08:32:05 +01:00
Eren Terzioglu
721c37a876 risc-v/esp32c6: Remove duplicated esp32c6 implementation 2024-01-30 08:32:05 +01:00
Yanfeng Liu
0f169f50c4 risc-v/k230: add big core support
Previously NuttX runs on little core of K230, this patch allows NuttX to
run on the big core as well.

Within folder `arch/risc-v/src/k230`:

- Changes:

    - CMakeLists.txt      add k230_hart.c to sources list
    - Make.defs           add k230_hart.c to sources list
    - chip.h              add inclusion to k230_hart.h etc
    - k230_irq.c          move sbi_late_init() to k230_hart.c
    - k230_start.c        add support to run on big core
    - hardware/:
      - k230_memorymap.h  add T-Head C908 specific CSR

- Additions:

    - k230_hart.c         sbi_late_init w/ hart initialization
    - k230_hart.h         header file

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-01-29 09:06:28 +01:00
raiden00pl
9d761b8ca4 arch/{nrf52|nrf53|nrf91}/tim.c: fix typo
fix offset for EVENT COMPARE0
2024-01-28 09:46:34 -08:00
Yanfeng Liu
f69f0674f6 arch/risc-v: add status fields for VS and XS
add defintions for vector extension and additional user-mode
extension fields for MSTATUS and SSTATUS registers.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-01-28 06:38:25 -08:00
ThomasNS
fff193324d xmc4 ccu4 register map 2024-01-27 20:14:02 -08:00
Yanfeng Liu
bb63f8f36d risc-v/canmv230: add CMake support
Adding CMakeLists.txt files to support CMake build system.
Note that only FLAT build works now due to limitations of current
CMake build system.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-01-27 00:56:57 -08:00
Benign X
8ba74d06c6 arch/sim: fix X11 compile failed 2024-01-27 00:51:32 -08:00
chenwen@espressif.com
ba1b96e9d9 xtensa/esp32s3: Add DMA peripheral to spi driver configuration
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
2024-01-26 19:14:04 -08:00
chenwen@espressif.com
8bef8ee9d5 xtensa/esp32s3: Fix crash issue that occurs when deleting a semaphore in WPA3
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
2024-01-26 04:45:26 -08:00
Takeyoshi Kikuchi
8571893435 arm: sama5: sam_serial: fix to compile with "UART Flow control enabled" on SAMA5D2.
SAMA5D2 has UART (TX/RX only) and FLEXCOM USART (with control pins).
UART has only TX/RX, so if I try to use flow control with FLEXCOM USART,
there is no register definition on the UART side and get a compilation error.

Signed-off-by: Takeyoshi Kikuchi <kikuchi@centurysys.co.jp>
2024-01-26 11:25:23 +08:00
Michal Lenc
addfa1c030 samv7: fix QSPI DMA option not showing in menuconfig
Commit 03e5c02 introduced option to have both standard SPI and QSPI
in SPI mode on one system. However this change broke the appearance of
QSPI driver configuration menu entry in menuconfig as it was dependent
on !SAMV7_QSPI_IS_SPI (which is now true for all MCUs having standard
SPI ability in QSPI driver).

This change makes sure the menu is correctly shown when QSPI driver
used.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2024-01-25 18:19:27 -08:00
raiden00pl
a12fdd8876 cosmetic changes after pci code rebase 2024-01-25 09:09:30 -08:00
raiden00pl
2e758f33ee fix various compilation errors after pci code rebase 2024-01-25 09:09:30 -08:00
Brennan Ashton
0ed4123326 x86_64: Early framebuffer console
This adds support for creating an early frame buffer and primatives for
writing to this frame buffer as a console. This does require the font
infrastructure as well as multiboot2.

Additionally this can now be used with a UEFI bootloader long as it
boots NuttX via Multiboot2.  There does seem to be a PCI interrupt
issue when running in UEFI mode.

I was able to boot my laptop using this and see PCI devices enumerate.

Signed-off-by: Brennan Ashton <bashton@brennanashton.com>

x86_64: Add conditionals around the multiboot framebuffer
2024-01-25 09:09:30 -08:00
Ville Juven
a188cf3480 mpfs_corespi: Fix firing of stale interrupt after warm reset
After warm reset the interrupt source in the HW block is not explicitly
cleared, thus once the interrupt source is enabled the old / stale interrupt
fires immediately.

This causes a DEBUGASSERT() failure on line 808 mpfs_spi_unload_rx_fifo:
  DEBUGASSERT(nwords > 0);
2024-01-25 11:23:12 -03:00
Tiago Medicci Serrano
c4f76ff867 esp32c3: Fix building native MCUboot from sources
This commit fixes building native MCUboot from sources by getting
the required sources from `esp-hal-3rdparty` repository and enable
building MCUboot and using it as the 2nd stage bootlaoder.
2024-01-25 11:22:39 -03:00
Tiago Medicci Serrano
a2673d3bcd esp32c3: Improve selection of the bootloader being used on Kconfig
- A pre-built IDF bootloader is used by default;
- `ESP32C3_PARTITION_TABLE` requires the IDF bootloader to be built
from sources.
- Native MCUboot also can be used to boot the device. It will be
built from sources and depends on !ESP32C3_PARTITION_TABLE.
2024-01-25 11:22:39 -03:00
Tiago Medicci Serrano
641a0df27f esp32s3: Improve selection of the bootloader being used on Kconfig
- A pre-built IDF bootloader is used by default;
- `ESP32S3_PARTITION_TABLE` requires the IDF bootloader to be built
from sources.
- Native MCUboot also can be used to boot the device. It will be
built from sources and depends on !ESP32S3_PARTITION_TABLE.
2024-01-25 11:22:39 -03:00
Tiago Medicci Serrano
1e1ea7bb5d esp32s2: Improve selection of the bootloader being used on Kconfig
- A pre-built IDF bootloader is used by default;
- `ESP32S2_PARTITION_TABLE` requires the IDF bootloader to be built
from sources.
- Native MCUboot also can be used to boot the device. It will be
built from sources and depends on !ESP32S2_PARTITION_TABLE.
2024-01-25 11:22:39 -03:00
Tiago Medicci Serrano
ec3714c816 esp32: Improve selection of the bootloader being used on Kconfig
- A pre-built IDF bootloader is used by default;
- `ESP32_PARTITION_TABLE` requires the IDF bootloader to be built
from sources.
- Native MCUboot also can be used to boot the device. It will be
built from sources and depends on !ESP32_PARTITION_TABLE.
2024-01-25 11:22:39 -03:00
Tiago Medicci Serrano
7ac14b544e risc-v/espressif: Select simple boot by default for RISC-V
Simple boot is a method of booting that doesn't depend on a 2nd
stage bootloader. Please note that some of the ESP-IDF bootloader
features are not available using simple boot, such as partition
tables and OTA: most of these features are implemented in NuttX
and MCUboot.
2024-01-25 11:22:39 -03:00
Michal Lenc
fba4b2593c samv7: refactor DAC driver
This commit refactors DAC driver. The functionality remains the same
but driver start up is now done in dac_setup (after application called
open function) instead of sam_dac_initialize (called from BSP). This
ensures that driver does not take resources (timer, interrupt) until
opened. Implementation of dac_shutdown is also provided, therefore
the driver frees resources once closed.

This change is consistent with other drivers implementation.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2024-01-24 18:46:33 -08:00
Michal Lenc
55ec92e181 samv7: add support for SPI mode in USART peripheral
USART peripheral can work in SPI mode as well. This commit adds support
for such functionality. Only 1 slave device is supported by the
peripheral therefore board level does not have to ensure correct CS
setup.

The usage of the peripheral is the same as with other SPI drivers.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2024-01-23 17:16:35 -03:00
chenwen@espressif.com
bdd02cc624 xtensa/esp32s3: Add APIs to release DMA channel resources
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
2024-01-23 17:16:16 -03:00
Almir Okato
f8b0b06b97 esp32c3-generic: add simple boot support
The Simple Boot feature for Espressif chips is a method of booting
that doesn't depend on a 2nd stage bootloader. Its not the
intention to replace a 2nd stage bootloader such as MCUboot and
ESP-IDF bootloader, but to have a minimal and straight-forward way
of booting, and also simplify the building.

This commit also makes this bootloader configuration as default
for esp32c3-generic target and removes the need for running
'make bootloader' command for it.

Signed-off-by: Almir Okato <almir.okato@espressif.com>
2024-01-23 04:09:25 -08:00
w2016561536
6b5ca79509 esp32s3/spi-dma: Fix spi dma transfer.
Fix esp32s3 spi dma transfer only transmit first byte and receive empty problem.
2024-01-23 04:05:52 -08:00
Lee Lup Yuen
62c358946d risc-v/bl808: Flush MMU Cache after updating SATP
Ox64 BL808 crashes with a Page Fault when we run `getprime` then `hello`. This is caused by the T-Head C906 MMU incorrectly accessing the MMU Page Tables of the Previous Process (`getprime`) while starting the New Process (`hello`).

To fix the problem, this PR flushes the MMU Cache whenever we point the MMU SATP Register to the New Page Tables. We execute 2 RISC-V Instructions that are specific to T-Head C906:

- DCACHE.IALL: Invalidate all Page Table Entries in the D-Cache
- SYNC.S: Ensure that all Cache Operations are completed

This is derived from the T-Head Errata for Linux Kernel. More details here: https://lupyuen.github.io/articles/mmu#appendix-flush-the-mmu-cache-for-t-head-c906

Modified Files:

- `arch/risc-v/src/common/riscv_mmu.h`: If needed, `mmu_write_satp()` calls `mmu_flush_cache()` (weak function) to flush the MMU Cache. (Like for T-Head C906)

- `arch/risc-v/src/bl808/bl808_mm_init.c`: Flush the MMU Cache for T-Head C906. Extend `mmuflags` from 32-bit to 64-bit to be consistent with `mmu_ln_setentry()`.

- `boards/risc-v/bl808/ox64/configs/nsh/defconfig`: Enable `ostest` in the Build Config. Update `CONFIG_BOARD_LOOPSPERMSEC` according to `calib_udelay`.
2024-01-23 01:25:20 -08:00
Yanfeng Liu
cba993df85 risc-v/cmake: add support to Ubuntu stock toolchain
Ubuntu stock toolchain `gcc-riscv64-unknown-elf` complains about
current CMake system (see issue#11573). This tries to fix it so
that both newer XPack and stock toolchains can be used with CMake.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-01-23 01:23:44 -08:00