sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity
41,509 Commits 1 Branch 0 Tags 291 MiB
db9c94962b
Commit Graph

17675 Commits

Author SHA1 Message Date
SPRESENSE
db9c94962b arch: cxd56xx: Add host interface driver 
Add host interface driver which supports I2C or SPI slave feature.
 2021-05-20 07:23:48 +02:00
SPRESENSE
5a7a118320 arch: cxd56xx: Fix uninitialized variable for gnss driver 
Fix uninitialized variable in gnss driver.
CodeSonar Warning 518288 - 518292
 2021-05-20 07:23:48 +02:00
SPRESENSE
151fec4e98 arch: cxd56xx: Do not re-initialize the console for subcore 
If the subcore configuration, which is mainly used in the Spresense
Arduino environment, is enabled, the serial console has been already
initialized by maincore. Then, don't need to re-initialize the UART1
serial driver.
 2021-05-20 07:23:48 +02:00
SPRESENSE
efd4789b72 arch: cxd56xx: gauge: Use the dedicated debug macro 
Replace to the battery dedicated debug macro instead of standard one.
 2021-05-20 07:23:48 +02:00
SPRESENSE
50cb0306b6 arch: cxd56xx: charger: Use the dedicated debug macro 
Replace to the battery dedicated debug macro instead of standard one.
 2021-05-20 07:23:48 +02:00
SPRESENSE
bb348cc464 arch: cxd56xx: gnss: Fix compile error in debug log 
Fix compile error when debug log is enabled.
Replace debug message from obsolete logerr() to _err().
 2021-05-20 07:23:48 +02:00
SPRESENSE
6d3fb9ee81 arch: cxd56xx: wdt: Fix compile error in debug log 
Fix compile error when CXD56_WDT_REGDEBUG is enabled.
 2021-05-20 07:23:48 +02:00
SPRESENSE
f0cae6cdf3 arch: cxd56xx: Fix multiple open and close ADC driver 
ADC driver does not support multiple open and close. It causes the memory
corruption by multiple free. This commit fixes this problem by introducing
the reference counter.
 2021-05-20 07:23:48 +02:00
SPRESENSE
98871e58af arch: cxd56xx: Fix gnss open error by clock change 
If the system clock is changed during loading gnssfw, gnss open may be
failed. So this commit prohibits clock change until loading gnssfw is
completed.
 2021-05-20 07:23:48 +02:00
SPRESENSE
e26da5f564 arch: cxd56xx: Update isop firmware 
Update isop firmware which supports for the error handling and i2c
multi-master environment.
 2021-05-20 07:23:48 +02:00
SPRESENSE
f548ffa7a7 arch: cxd56xx: Support execution error by SCU sequencer 
Enable interrupt by SCU sequencer execution error. If the interrupt
occurs, then it stops the sequencer and returns the error code.
 2021-05-20 07:23:48 +02:00
SPRESENSE
ba6201401f arch: cxd56xx: Remove unnecessary i2c settings 
Remove slave address register setting that is unnecessary for the
transfer by SCU sequencer.
 2021-05-20 07:23:48 +02:00
SPRESENSE
ade26c17d2 arch: cxd56xx: Update i2c register initialization 
Enable RX_FIFO_FULL_HLD_CTRL and RESTART of i2c control register in
i2c initial settings for transfer by SCU sequencer.
 2021-05-20 07:23:48 +02:00
SPRESENSE
a10a4c483f arch: cxd56xx: Add SCU register definitions 
Add SCU register definitions.
 2021-05-20 07:23:48 +02:00
SPRESENSE
09cc6b780b arch: cxd56xx: update loader and gnssfw version 
Update loader and gnssfw to version 2.2.20175
 2021-05-20 07:23:48 +02:00
SPRESENSE
a276de741f arch: cxd56xx: Fix SPI setmode function 
When SSP mode is changed, SSE bit of SSPCR1 register must be disabled.
 2021-05-20 07:23:48 +02:00
SPRESENSE
89fd987a1a arch: cxd56xx: Fix RTC alarm cancellation process 
There is an issue that the next alarm is expired immediately after
canceling a RTC alarm. Fixed alarm settings to be completely cleared
when canceling an RTC alarm.
 2021-05-20 07:23:48 +02:00
SPRESENSE
67a56410ee arch: cxd56xx: Prohibit clock change during SPI transfer 
If the system clock is changed during the SPI transfer, the SPI data can
be corrupted. So this commit prohibits the clock change during SPI transfer,
and keep the clock until the transfer is completed.
 2021-05-20 07:23:48 +02:00
SPRESENSE
db340a8941 arch: cxd56xx: Support for suppresion of clock change 
Introduce PM_CPUFREQLOCK_FLAG_HOLD into the frequency lock mechanism in
power manager, which is used to keep the current frequency without clock
change, for example, during the transfer of a periphral.
 2021-05-20 07:23:48 +02:00
SPRESENSE
9b3a80cc37 arch: cxd56xx: Fix uart getting stuck during a clock change 
UART driver is stopped and re-started during a clock change. When a UART
interrupt is generated in each process, the unexpected behavior will
occur and a console will get stuck with UART driver. This commit fixed
each process is performed atomically.
 2021-05-20 07:23:48 +02:00
jordi
ccc8c078f9 xtensa/esp32: Fix warning "is not defined" 
Detected with "-Werror" flag
 2021-05-19 20:03:03 +01:00
Anthony Merlino
e37ce7677b Try to address CI build error and a few macro fixes. 2021-05-19 10:41:18 -07:00
Anthony Merlino
b54a4c7788 Replace more ATIM_/BTIM_ macros with GTIM_ macros 2021-05-19 10:41:18 -07:00
Anthony Merlino
58c92be39c stm32 timers: Make some register operations more readable. 2021-05-19 10:41:18 -07:00
chenwen
9a99d813fa risc-v/esp32c3: Support ESP32-C3 auto-sleep 2021-05-19 07:00:40 -03:00
Chen Wen
e44ec9e48e xtensa/esp32: Fix code nxstyle issue 2021-05-19 06:45:42 -03:00
chenwen
f7db743152 xtensa/esp32: Support auto-sleep 2021-05-19 06:45:42 -03:00
chenwen
f50160f0e1 xtensa/esp32: Support tick-less OS 2021-05-19 06:45:42 -03:00
Abdelatif Guettouche
65e9ff5a48 xtensa/esp32/esp32_start.c: Remove an old and unnecessary piece of code. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-05-19 03:05:52 -05:00
Dong Heng
f12de4f7d9 riscv/esp32c3: Add ESP32-C3 ADC driver 2021-05-18 09:20:46 -03:00
Gustavo Henrique Nihei
26a5cb2094 risc-v/esp32c3: Add support for DMA transfers on SPI driver 2021-05-17 13:21:12 +01:00
Gustavo Henrique Nihei
132ffdd28d risc-v/esp32c3: Add burst transfer support for GDMA 2021-05-17 13:21:12 +01:00
Dong Heng
4a7f998c33 riscv/esp32c3: Fix RT timer issues 
1. Enable alarm if there is timer active
2. Wake up main thread to delete timer
3. Wake up main thread when timer is timeout in ISR
 2021-05-16 13:23:43 -05:00
Anthony Merlino
fa2b9ca43b stm32/stm32f7 tickless: Fix up_timer_getmask to be correct for the width of the timer. 2021-05-16 13:04:31 -05:00
Anthony Merlino
99a9d75cdd stm32f7: Remove references to BOARD_ENABLE_USBOTG_HSULPI. Prefer Kconfig option instead. 2021-05-16 01:02:51 -07:00
Jiuzhu Dong
73cc1f8884 driver/rtc: add config CONFIG_RTC_RPMSG_SERVER to 
N/A
select rtc rpmsg role.

Change-Id: I7f9053b070593573caa5d988c6a2e13593da6bc5
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2021-05-15 14:33:52 -03:00
Jiuzhu Dong
f082893b9a driver/rtc: add config RTC_RPMSG_SERVER_NAME to 
specified the name of remote proc(rpmsg server)

Change-Id: I0086bb43727a2bbb5e68f88907b5e4608182ef9c
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2021-05-15 14:33:52 -03:00
Jiuzhu Dong
ff567124d3 driver/syslog: add config SYSLOG_RPMSG_SERVER_NAME to 
N/A

specified the name of remote proc(rpmsg server)

Change-Id: Ie270d651071e87a40a80ab489597ae18db9814f0
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2021-05-15 09:39:57 -03:00
Dong Heng
beed26b6bf riscv/esp32c3: Add ESP32-C3 LEDC(PWM) driver 2021-05-15 08:38:37 -03:00
chenwen
16667930cb risc-v/esp32c3: Support ESP32-C3 PM standby and sleep 2021-05-12 10:15:06 -03:00
Juha Niskanen
abcb67a292 Remove final remaining CONFIG_DISABLE_SIGNALS and CONFIG_DISABLE_SIGNAL 2021-05-10 17:04:38 -03:00
Nathan Hartman
8af9d39667 Documentation, comments: Minor improvements and typos fixed 2021-05-09 19:12:13 -07:00
David Sidrane
17b786399c stm32:SDIO:Use 250 Ms Data path timeout, regardless of Card Clock frequency 2021-05-07 17:39:08 -04:00
David Sidrane
3e49d49cd9 stm32h7:SDMMC:Use 250 Ms Data path timeout, regardless of Card Clock frequency 2021-05-07 17:39:08 -04:00
David Sidrane
c45e03b75f stm32f7:SDMMC:Use 250 Ms Data path timeout, regardless of Card Clock frequency 2021-05-07 17:39:08 -04:00
Gustavo Henrique Nihei
90a4e8d718 risc-v/esp32c3: Fix DMA channels' interrupt IDs 2021-05-07 16:46:41 -03:00
Dong Heng
bd8e37bb4b risc-v/esp32c3: Add ESP32-C3 (G)DMA driver and testing 2021-05-07 16:46:41 -03:00
Harri Luhtala
e5f1069654 arch/arm/src/stm32l4/hardware/stm32l4xrxx: pinmap alternative function for SPI2 2021-05-07 05:08:05 -07:00
Raman Gopalan
9044594545 at32uc3_gpioirq.c: Fix typo: contex -> context 2021-05-06 11:25:38 -03:00
Gustavo Henrique Nihei
534c058d93 spi: Adopt CPHA as the abbreviation for clock phase 2021-05-05 16:56:07 -03:00