Matrix.
This allows manipulating interrupts from both CPUs. Internal interrupts
however, still need to be disabled/enabled by each CPU.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
They do the same thing (manipulate interrupts) keeping them separated
was making things harder.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
Allocating and attaching interrupts were both exported outside, however
these two move hand in hand and we don't have to expose these details.
Also, the parameters passed are saved and will be used to retrieve
information about the interrupt and the attached peripheral.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
interrupt.
That function will have a parameter to decide whether to allocate a
level sensitive interrupt or an edge sensitive interrupt.
All the drivers are also updated with this API change.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
are do not go through the regular process where we attache the CPU
interrupt to a peripheral and update our map, also, they are fixed and a
have reserved CPU interrupt, thus hard code their values at startup.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
At this point we are in a critical section and have all the necessary
information to disable the interrupt properly (CPU, and CPU interrupt).
Leaving it to the drivers will complicate things as converting from IRQs
to CPU interrupts could be tricky in SMP mode.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
This map also keeps track of the CPU that attached the IRQ. This will
be used to properly disable the interrupt in the correct CPU in SMP
mode.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
ESP32 uses a different function to start the app CPU and no other xtensa
CPU uses this __cpu1_start function.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
Consider follow coprocessor configuration case:
\#define XCHAL_CP_NUM 1 /* number of coprocessors */
\#define XCHAL_CP_MAX 2 /* max CP ID + 1 (0 if none) */
\#define XCHAL_CP_MASK 0x02 /* bitmask of all CPs by ID */
\#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
\
\#define XCHAL_CP1_NAME "AudioEngineLX"
\#define XCHAL_CP1_IDENT AudioEngineLX
\#define XCHAL_CP1_SA_SIZE 208 /* size of state save area */
\#define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */
\#define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
In this case, XTENSA_CP_ALLSET is 0x1, but valid coprocessors
bitmap is 0x2, use marco XCHAL_CP_MASK instead, it is bitmap of all
vaild coprocs.
Change-Id: I63ec01e4bd0cbafc62d56636cc11bdc4a2f7857f
Many duplicate code when more chips add-in,
follow arch/arm/include/irq.h method, use chip/irq.h instead.
Change-Id: I42f516c1dda68e973939c669f627c457cd0bc65e
In levelx(2,3,4,5)_handler, first need to save sp in a12,
then after dispatch_c_isr we can restore sp from a12.
Change-Id: Idb6b64a782da866670a4db80b33435a9b63f02c3
Some toolchain such as xtensa-xcc is unrecognize with constraint letter 'I',
letter 'i' is more common in GNU assembler.
Change-Id: I00f6a33fd7a5f2b95508c683e9954d402b68755f
In config with no "CONFIG_SPINLOCK", include arch/spinlock.h will lead to
build error as multi definition with spinlock_t. Nuttx/spinlock.h will
include arch/spinlock.h when needed.
Change-Id: I33b48503f679ec79af3a0ef1f0fb1536aaf1ce7c
Currently the "esp32_spiflash_alloc_mtdpart" allocates a
statically-defined partition from "offset" and "size" set via
Kconfig.
This commit changes the function interface to receive those information
as arguments, enabling the creation of multiple MTD partitions with
different offsets and sizes.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
