1.add pin type to cfg gpio as wake up source
2.add IOEXPANDER_OPTION_WAKEUPCFG for set wake up option
Signed-off-by: dulibo1 <dulibo1@xiaomi.com>
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
and move common math funtions to math32.h:
div_round_up
div_round_closest
is_power_of_2
roundup_pow_of_two
rounddown_pow_of_two
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
When the toolchain does not support atomic, it will use the version implemented by NuttX (low performance version). This scenario is consistent with the original design, so we can ignore it.
see bug here:
https://bugs.llvm.org/show_bug.cgi?id=43603
Error: inode/fs_inodeaddref.c:50:7: error: large atomic operation may incur significant performance penalty; the access size (4 bytes) exceeds the max lock-free size (0 bytes) [-Werror,-Watomic-alignment]
50 | atomic_fetch_add(&inode->i_crefs, 1);
| ^
/tools/clang-arm-none-eabi/lib/clang/17/include/stdatomic.h:152:43: note: expanded from macro 'atomic_fetch_add'
152 | #define atomic_fetch_add(object, operand) __c11_atomic_fetch_add(object, operand, __ATOMIC_SEQ_CST)
| ^
1 error generated.
make[1]: *** [Makefile:83: fs_inodeaddref.o] Error 1
Error: inode/fs_inodefind.c:74:7: error: large atomic operation may incur significant performance penalty; the access size (4 bytes) exceeds the max lock-free size (0 bytes) [-Werror,-Watomic-alignment]
74 | atomic_fetch_add(&node->i_crefs, 1);
Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
Summary:
1.Modified the i_crefs from int16_t to atomic_int
2.Modified the i_crefs add, delete, read, and initialize interfaces to atomic operations
The purpose of this change is to avoid deadlock in cross-core scenarios, where A Core blocks B Core’s request for a write operation to A Core when A Core requests a read operation to B Core.
Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
This commit added ifdef macro to sigwork_s. When CONFIG_SIG_EVTHREAD is
not defined, the struct sigwork_s will be empty struct, which is helpful
to reduce bss size.
Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
This commit simplified thread ID dispatching logic by integrating it into the `nxsig_dispatch` function.
Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
continue work of f76c2ed83b
detail: Add g_ prefix to can_dlc_to_len and len_to_can_dlc to
follow NuttX coding style conventions for global symbols,
improving code readability and maintainability.
Signed-off-by: chao an <anchao@lixiang.com>
1. cpufreq.h not found if cpufreq is not supported on some branches.
./thermal/thermal_dummy.c:25:10: fatal error: nuttx/cpufreq.h: No such file or directory
25 | #include <nuttx/cpufreq.h>
| ^~~~~~~~~~~~~~~~~
compilation terminated.
2. debug.h is included by including <nuttx/cpufreq.h>, should not.
CC: thermal/thermal_dummy.c thermal/thermal_dummy.c: In function ‘thermal_dummy_init’:
thermal/thermal_dummy.c:338:7: warning: implicit declaration of function ‘therr’ [-Wimplicit-function-declaration]
338 | therr("Register cooling device fan0 failed!\n");
|
https://github.com/apache/nuttx/pull/12824
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
When exec "echo 1 > /proc/thermal/cpu-thermal", procfs get "\n" after "1", treat as disable:
```
#1 0x000000000040f452 in thermal_procfs_write (filep=0x7ffff3d241e8, buffer=0x7ffff3d344fc "\n", buflen=1) at thermal/thermal_procfs.c:179
```
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
The aforementioned functions can/will fail if the C compiler decides
to use the stack for the incoming entrypt/etc. parameters.
Fix this issue by converting the jump to user part into pure assembly,
ensuring the stack is NOT used for the parameters.
When its remote core publishes a message, all subscribed cores will receive the message,
but the local core "stublist" does not update the user's "generation" and "bufferpos" parameters.
Signed-off-by: likun17 <likun17@xiaomi.com>
The original code made the incorrect assumption that the amount of
translation levels is 3, but this is incorrect. The amount of levels is 4
and the amount of levels that are utilized / in use is set dynamically
from the amount of VA bits in use.
The VMSAv8-64 translation system has 4 page table levels in total, ranging
from 0-3. The address environment code assumes only 3 levels, from 1-3 but
this is wrong; the amount of levels _utilized_ depends on the configured
VA size CONFIG_ARM64_VA_BITS. With <= 39 bits 3 levels is enough, while
if the va range is larger, the 4th translation table level is taken into
use dynamically by shifting the base translation table level.
From arm64_mmu.c, where va_bits is the amount of va bits used in address
translations:
(va_bits <= 21) - base level 3
(22 <= va_bits <= 30) - base level 2
(31 <= va_bits <= 39) - base level 1
(40 <= va_bits <= 48) - base level 0
The base level is what is configured as the page directory root. This also
affects the performance of address translations i.e. if the VA range is
smaller, address translations are also faster as the page table walk is
shorter.
This defconfig is an example of the recorded stack and it became
faulty recently after the implementation of the `up_current_regs`
functions. The `noinstrument_function` directive must be used for
preventing it from being looped when instrumentation is enabled.
Also, this commit places `sched/instrument/stack_record.c` in IRAM.
with other functionalities removed.
reason:
by doing this we can reduce context switch time,
When we exit from an interrupt handler, we directly use tcb->xcp.regs
before
text data bss dec hex filename
138805 337 24256 163398 27e46 nuttx
after
text data bss dec hex filename
138499 337 24240 163076 27d04 nuttx
szie change -322
Signed-off-by: hujun5 <hujun5@xiaomi.com>
