Bug description:
CONFIG_SMP=y
Suppose we have 2 cores in SMP, here is the ps return:
PID GROUP CPU PRI POLICY TYPE NPX STATE STACK USED FILLED COMMAND
0 0 0 0 FIFO Kthread N-- Assigned 004076 000748 18.3% CPU0 IDLE
1 0 1 0 FIFO Kthread N-- Running 004096 000540 13.1% CPU1 IDLE
nsh> kill -4 0
or:
nsh> kill -4 1
system blocked.
Reason:
In func xx_sigdeliver() restore stage, when saved_irqcount == 0, that means
rtcb NOT in critical_section before switch to xx_sigdeliver(), then we need
reset the critical_section state before swith back.
Fix:
Add condition to cover saved_irqcount == 0.
Change-Id: I4af7f95e47f6d78a4094c3757d39b01ac9d533b3
Signed-off-by: ligd <liguiding1@xiaomi.com>
since there are situation which send singal to idle thread already,
CONFIG_SCHED_CHILD_STATUS=y
CONFIG_SCHED_HAVE_PARENT=y
Signo SIGCHLD will send to parent group, when child exit
Change-Id: Iceb2ac41948c1c3418839a3b5de70985d48c75d1
Signed-off-by: ligd <liguiding1@xiaomi.com>
adds CONFIG_AUDIO_FORMAT_RAW as an option to the PCM
audio format for devices expecting raw data without
a header.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
This Knob will cycle through the values from
low to high. To avoid damaging the crystal.
We want to use the lowest setting that gets
the OSC running. See app note AN2867
This Knob will cycle through the correct*
values from low to high. To avoid damaging
the crystal. We want to use the lowest setting
that gets the OSC running. See app note AN2867
*It will take into account the rev of the silicon
and use the correct code points to achive the drive
strength. See Eratta ES0392 Rev 7 2.2.14 LSE oscillator
driving capability selection bits are swapped.
Summary:
- During investigating critical section with semaphores, I noticed
that nxtask_flushstreams() is called with a critical section.
- The function calls lib_flushall() which handles a semaphore
in userspace.
- So it should be done without a critical section
Impact:
- SMP only
Testing:
- Tested with ostest the following configs
- esp32-devkitc:smp (QEMU), sabre-6quad:smp (QEMU)
- maix-bit:smp (QEMU), sim:smp
- spresense:smp
- Tested with nxplayer and stress test with spresense:wifi_smp
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Change the copyright header of assorted source files in libs/libc to the
ASF version. I was listed as the author in these files. I did also
check the heritage of those files and besides me they have only been
changed by the following people, all of whom did sign a CLA to the best
of my knowledge:
Alin Jerpelea
Haitao Liu
Gregory Nutt
Yamamoto Takashi
Xiang Xiao
Signed-off-by: Michael Jung <mijung@gmx.net>
With TrustZone support in armv8-m the bit-fields in EXC_RETURN have been
extended. Bit 6 ('S') now specifies whether the interrupted program was
running in the Non-Secure (S=0) or Secure (S=1) security state.
Furthermore, Bit 0 ('ES' - Exception Secure) specifies the
security state athe exception is taken to (0: Non-Secure, 1: Secure).
When NuttX is run together with TrustedFirmware-M as the application in
the non-secure world both the S and the ES bits have to be set to '0'.
For armv8-m those are also the correct values if TrustZone is not
implemented on the respective MCU or if it is disabled.
Signed-off-by: Michael Jung <mijung@gmx.net>
This seems to fix esp32_readdata_encrypted() with spiram "buffer".
Note: I'm not sure if this is the right fix or not.
I couldn't find any documentation about Cache_Flush.
Summary:
- The code was added in Mar 2018 to stabilize the SMP kernel
- I confirmed that the code is no longer needed now.
Impact:
- SMP only
Testing:
- Tested with ostest the following configs
- esp32-devkitc:smp (QEMU), sabre-6quad:smp (QEMU)
- maix-bit:smp (QEMU), sim:smp
- spresense:smp
- Tested with nxplayer and stress test with spresense:wifi_smp
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- Adjust CONFIG_BOARD_LOOPSPERMSEC in all defconfigs
- Add CONFIG_TESTING_GETPRIM to nsh and nshsram
- Add CONFIG_SYSTEM_TASKSET to smp
- NOTE: CONFIG_SCHED_WAITPID is removed because it is selected
Impact:
- The smp app will take longer than before but it's a correct behavior
Testing:
- Tested with getprime, ostest, smp
Summary:
- This commit applies armv7-m signal handling logic
Impact:
- armv6-m signal handling
Testing:
- Tested with ostest with the following configs
- raspberrypi-pico:nsh, raspberrypi-pico:smp
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
IRQs cannot be individually disabled on the eZ80, so using
`up_disable_irq()` had no effect. This left the IRQ handler being
constantly triggered without the lower half handler running.
The macro for EMAC stats was incompatible with Clang. The simplified
form gives identical results under ZDS-II.
The MII clock speed must be set before trying to read MII registers.
It's now done before resetting the PHY using the Mode Control Register.
MII initialization waited on the auto-neogotiate restart bit being set
but PHY hardware is frequently fast enough to have cleared the bit
before the first read of it. It now instead just waits on auto-negotiate
completing. The MII poll loop now uses `up_mdelay` because it was far
too fast at 50MHz using a busy loop, giving time for a link to be
established.
Bad packets are now processed enough to release their buffers back to
the EMAC hardware.
A few typos, unused variables, and other miscellaneous issues were also
fixed.
