The text describes an issue related to the running task in code.
The running task is only used when calling the _assert function
to indicate the task that was running before an exception occurred.
However, the current code only updates the running task during
irq_dispatch, which is suitable for ARM-M architecture but not
for ARM-A or ARM-R architecture, because their context switches
are not done through irq handler. Therefore, if the following
process is followed, the value of the running task will be incorrect:
1. task1 is running, this_task()=task1
2. do_irq is executed, setting running task()=task1
3. task1 switches to task2
4. task2 is running and generates a data abort
5. In the data abort, the _assert function is called,
and the running task obtained is still task1, but
the actual task that generated the exception is task2.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
Problem:
AppBringup task in default priority 240 ->
board_late_initialize() ->
some driver called work_queue() ->
nxsem_post(&(wqueue).sem) failed because sem_count is 0
hp work_thread in default priority 224 ->
nxsem_wait_uninterruptible(&wqueue->sem);
so hp_work_thread can't wake up, worker can't run immediately.
Signed-off-by: dongjiuzhu1 <dongjiuzhu1@xiaomi.com>
If this option is enabled, the working path of nuttx will be modified to the folder where the nuttx file is located.
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
Over-drive can be forced to a given state by adding define to the
board.h configuration file:
#define STM32_VOS_OVERDRIVE 1 - force over-drive enabled,
#define STM32_VOS_OVERDRIVE 0 - force over-drive disabled,
#undef STM32_VOS_OVERDRIVE - autoselect over-drive by the default RCC logic
It seems that over-drive is not required for ULPI but it can be a workaround solution for boards with poor signal integration.
Higher core voltage means faster clock signal edges, which may be sufficient to synchronize the high-speed clock and data on poorly designed boards.
Over-drive can be forced to a given state by adding define to the
board.h configuration file:
#define STM32_VOS_OVERDRIVE 1 - force over-drive enabled,
#define STM32_VOS_OVERDRIVE 0 - force over-drive disabled,
#undef STM32_VOS_OVERDRIVE - autoselect over-drive by the default RCC logic
It's better to raise error before client sends its (NIOVEC+1)th buffer
(and release buffers held by server), otherwise the client may stuck at
getting (NIOVEC+1)th tx buffer if NIOVEC is equal to rpmsg buffer num.
Signed-off-by: Zhe Weng <wengzhe@xiaomi.com>
Found a problem:
When sendto handler gets an error, it will release all its rx buffer,
then iov_base becomes NULL. But it cannot let client stop its request,
then the next data from client cannot be handled by usrsock server
correctly.
It's better to note down the remaining bytes, then we can stop at
correct time.
Signed-off-by: Zhe Weng <wengzhe@xiaomi.com>
- Remove the temporary "saved" variable when temporarily changing MMU
mappings to access another process's memory. The fact that it has an
address environment is enough to make the choice
- Restore nxflat_addrenv_restore-macro. It was accidentally lost when
the address environment handling was re-factored.
The Inter-Processor Interrupt that pauses the other CPU generates
a level-1 interrupt which sets the PS.EXCM. This level-1 interrupt
is treated as an Exception and the bit PS.EXCM bit is automatically
reset on return from Exception. However, this is not the case here
because we are changing the execution to the signal trampoline.
Restoring the PS register with the PS.EXCM bit set would cause any
other exception to deviate execution to the DEC (double exception
vector), avoiding it to be treated correctly. According to the
xtensa ISA: "The process of taking an interrupt does not clear
the interrupt request. The process does set PS.EXCM to 1, which
disables level-1 interrupts in the interrupt handler. Typically,
the PS.EXCM is reset to 0 by the handler, after it has set up the
stack frame and masked the interrupt." Clean the saved PS.EXCM to
1) avoid an exception from being properly treated and 2) avoid
interrupts to be masked while delivering the signal.
This is a workaround commit to temporarily reduce the flash usage of
esp32c6 to avoid ci failure, Since I am not familiar with esptool,
and this issue cannot be reproduced in the local environment,
so I temporarily turn off related optimizations to save flash size.
esptool error log:
-----------------------------------------
| MKIMAGE: ESP32-C6 binary
| esptool.py --chip esp32c6 elf2image --flash_mode dio --flash_size "4MB" -o nuttx.bin nuttx
| esptool.py v4.5.1
| Creating esp32c6 image...
| Merged 1 ELF section
|
| A fatal error occurred: Segment loaded at 0x42010c08 lands in same 64KB flash mapping as segment loaded at 0x42010020. Can't generate binary. Suggest changing linker script or ELF to merge sections.
| make: *** [tools/Unix.mk:527: nuttx] Error 2
| make: Target 'all' not remade because of errors.
-----------------------------------------
Signed-off-by: chao an <anchao@xiaomi.com>
In the previous implementation, PerformanceCounter would cause overflow
after running for a long time, This commit will separate the calculation
of the sec/ms part to avoid this issue, Reference:
https://github.com/cygwin/cygwin/blob/main/winsup/cygwin/clock.cc#L194-L217
Signed-off-by: chao an <anchao@xiaomi.com>
Add header keywords into whitelist, skip the warning if the
particular headers will contain the functions with mixed case
Signed-off-by: chao an <anchao@xiaomi.com>
- The code will detect an error condition described in
https://cwiki.apache.org/confluence/display/NUTTX/Signaling+Semaphores+and+Priority+Inheritance
- The kernel will go to PANIC if semaphore holder can't be allocated even
if CONFIG_DEBUG_ASSERTIONS is disabled
- Clean-up code that handled posing of semaphore with priority inheritance
enabled from the interrupt context (remove nxsem_restore_baseprio_irq())
On a GICv2 implementation, setting GICC_CTLR.EOImode to 1 separates
the priority drop and interrupt deactivation operations.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
Summary:
- Support arm64 pmu api, Currently only the cycle counter function is supported.
- Using ARM64 PMU hardware capability to implement perf interface, modify all
perf interface related code.
- Support for pmu init under smp.
Signed-off-by: wangming9 <wangming9@xiaomi.com>
After enabling this option, you can automatically trace the function instrumentation without adding tracepoint manually.
This is similar to the Function Trace effect of the linux kernel
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
