Abdelatif Guettouche eb403bc996 boards/riscv/esp32c3: Rename the iram_0_2 segment to irom_0_0 to avoid ...

confusions.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>

2021-06-24 07:00:51 -05:00

..

.gitignore

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esp32c3_rom.ld

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esp32c3.ld

arch/risc-v/esp32c3: Use the same naming for the RTC heap as ESP32 for

2021-06-23 08:37:01 +09:00

esp32c3.template.ld

boards/riscv/esp32c3: Rename the iram_0_2 segment to irom_0_0 to avoid

2021-06-24 07:00:51 -05:00

gnu-elf.ld

boards/risc-v/esp32c3-devkit: Add an ELF defconfig and the necessary ELF

2021-06-04 18:08:36 -03:00

Make.defs

boards/esp32c3-devkit: Add the necessary flags for loadable modules and

2021-06-04 18:08:36 -03:00