120 lines
3.8 KiB
C
120 lines
3.8 KiB
C
/****************************************************************************
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* boards/arm/sam34/sam4s-xplained/src/sam_sram.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <debug.h>
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#include "arm_internal.h"
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#include "sam4s_periphclks.h"
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#include "hardware/sam_smc.h"
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#include "sam4s-xplained.h"
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#ifdef CONFIG_SAM34_EXTSRAM0
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define NPINS (3+8+19+1)
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/****************************************************************************
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* Private Data
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****************************************************************************/
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static const gpio_pinset_t g_srampins[NPINS] =
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{
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GPIO_SMC_NCS0, GPIO_SMC_NRD, GPIO_SMC_NWE,
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GPIO_SMC_D0, GPIO_SMC_D1, GPIO_SMC_D2, GPIO_SMC_D3,
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GPIO_SMC_D4, GPIO_SMC_D5, GPIO_SMC_D6, GPIO_SMC_D7,
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GPIO_SMC_A0, GPIO_SMC_A1, GPIO_SMC_A2, GPIO_SMC_A3,
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GPIO_SMC_A4, GPIO_SMC_A5, GPIO_SMC_A6, GPIO_SMC_A7,
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GPIO_SMC_A8, GPIO_SMC_A9, GPIO_SMC_A10, GPIO_SMC_A11,
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GPIO_SMC_A12, GPIO_SMC_A13, GPIO_SMC_A14, GPIO_SMC_A15,
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GPIO_SMC_A16, GPIO_SMC_A17, GPIO_SMC_A18,
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GPIO_EBI_NLB
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};
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: sam_sram_initialize
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*
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* Description:
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* Configure and enable SRAM on board the SAM4S Xplained
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*
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****************************************************************************/
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void sam_sram_initialize(void)
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{
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int i;
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/* Configure GPIO pins (leaving SRAM in the disabled state) */
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for (i = 0; i < NPINS; i++)
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{
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sam_configgpio(g_srampins[i]);
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}
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/* Enable PMC clock to the SMC */
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sam_smc_enableclk();
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/* Configure SMC setup timing */
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putreg32(SMCCS_SETUP_NWESETUP(1) | SMCCS_SETUP_NCSWRSETUP(1) |
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SMCCS_SETUP_NRDSETUP(1) | SMCCS_SETUP_NCSRDSETUP(1),
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SAM_SMCCS0_SETUP);
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/* Configure the SMC pulse timing */
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putreg32(SMCCS_PULSE_NWEPULSE(6) | SMCCS_PULSE_NCSWRPULSE(6) |
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SMCCS_PULSE_NRDPULSE(6) | SMCCS_PULSE_NCSRDPULSE(6),
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SAM_SMCCS0_PULSE);
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/* Configure the SMC cycle timing */
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putreg32(SMCCS_CYCLE_NWECYCLE(7) | SMCCS_CYCLE_NRDCYCLE(7),
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SAM_SMCCS0_CYCLE);
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/* Configure the SMC mode */
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putreg32(SMCCS_MODE_READMODE | SMCCS_MODE_WRITEMODE, SAM_SMCCS0_MODE);
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/* Enable SRAM access (active low) */
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sam_gpiowrite(GPIO_EBI_NLB, false);
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}
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#endif /* CONFIG_SAM34_EXTSRAM0 */
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